- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄374864 > SN74ALVC7806DL (Texas Instruments, Inc.) 256 】 18 LOW-POWER FIRST-IN, FIRST-OUT MEMORY PDF資料下載
參數(shù)資料
| 型號(hào)： | SN74ALVC7806DL |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 256 】 18 LOW-POWER FIRST-IN, FIRST-OUT MEMORY |
| 中文描述： | 256】18 LOW-POWER先入先出存儲(chǔ)器 |
| 文件頁數(shù)： | 1/10頁 |
| 文件大小： | 138K |
| 代理商： | SN74ALVC7806DL |
SN74ALVC7806
256
×
18
LOW-POWER FIRST-IN, FIRST-OUT MEMORY
SCAS591A – OCTOBER 1997 – REVISED APRIL 1998
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Member of the Texas Instruments
Widebus
Family
Low-Power Advanced CMOS Technology
Operates From 3-V to 3.6-V V
CC
Load Clock and Unload Clock Can Be
Asynchronous or Coincident
Full, Empty, and Half-Full Flags
Programmable Almost-Full/Almost-Empty
Flag
Fast Access Times of 18 ns With a 50-pF
Load and All Data Outputs Switching
Simultaneously
Data Rates up to 40 MHz
3-State Outputs
Pin-to-Pin Compatible With SN74ACT7804,
SN74ACT7806, and SN74ACT7814
Packaged in Shrink Small-Outline 300-mil
Package Using 25-mil Center-to-Center
Spacing
description
A FIFO memory is a storage device that allows
data to be written into and read from its array at
independent data rates. The SN74ALVC7806 is
an 18-bit FIFO with high speed and fast access
times. Data is processed at rates up to 40 MHz
with access times of 18 ns in a bit-parallel format.
These memories are designed for 3-V to 3.6-V
V
CC
operation.
Data is written into memory on a low-to-high
transition of the load clock (LDCK) and is read out
on a low-to-high transition of the unload clock
(UNCK). The memory is full when the number of words clocked in exceeds the number of words clocked out
by 256. When the memory is full, LDCK has no effect on the data residing in memory. When the memory is
empty, UNCK has no effect.
Status of the FIFO memory is monitored by the full (FULL), empty (EMPTY), half-full (HF), and almost-
full/almost-empty (AF/AE) flags. The FULL output is low when the memory is full and high when the memory
is not full. The EMPTY output is low when the memory is empty and high when it is not empty. The HF output
is high whenever the FIFO contains 128 or more words and low when it contains 127 or fewer words. The AF/AE
status flag is a programmable flag. The first one or two low-to-high transitions of LDCK after reset are used to
program the almost-empty offset value (X) and the almost-full offset value (Y) if program enable (PEN) is low.
The AF/AE flag is high when the FIFO contains X or fewer words or (256 – Y) or more words. The AF/AE flag
is low when the FIFO contains between (X + 1) and (255 – Y) words.
Copyright
1998, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Widebus is a trademark of Texas Instruments Incorporated.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
RESET
D17
D16
D15
D14
D13
D12
D11
D10
V
CC
D9
D8
GND
D7
D6
D5
D4
D3
D2
D1
D0
HF
PEN
AF/AE
LDCK
NC
NC
FULL
OE
Q17
Q16
Q15
GND
Q14
V
CC
Q13
Q12
Q11
Q10
Q9
GND
Q8
Q7
Q6
Q5
V
CC
Q4
Q3
Q2
GND
Q1
Q0
UNCK
NC
NC
EMPTY
DL PACKAGE
(TOP VIEW)
NC – No internal connection
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SN74ALVC7813DL | 64 】 18 LOW-POWER CLOCKED FIRST-IN, FIRST-OUT MEMORY |
| SN74ALVC7814DL | 64 】 18 LOW-POWER FIRST-IN, FIRST-OUT MEMORY |
| SN74ALVCF162835DLR | 3.3-V CMOS 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS |
| SN74ALVCF162835LR | Ceramic Chip Capacitors / MIL-PRF-55681; Capacitance [nom]: 1300pF; Working Voltage (Vdc)[max]: 50V; Capacitance Tolerance: +/-10%; Dielectric: Multilayer Ceramic; Temperature Coefficient: C0G (NP0); Lead Style: Surface Mount Chip; Lead Dimensions: 1206; Termination: 100% Tin (Sn); Body Dimensions: 0.125" x 0.062" x 0.051"; Container: Bag; Features: MIL-PRF-55681: S Failure Rate |
| SN74ALVCH162244DGG | 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SN74ALVC7813-20DL | 功能描述:先進(jìn)先出 16-Bit Bus Trnscvr With 3-State Outputs RoHS:否 制造商:IDT 電路數(shù)量: 數(shù)據(jù)總線寬度:18 bit 總線定向:Unidirectional 存儲(chǔ)容量:4 Mbit 定時(shí)類型:Synchronous 組織:256 K x 18 最大時(shí)鐘頻率:100 MHz 訪問時(shí)間:10 ns 電源電壓-最大:3.6 V 電源電壓-最小:6 V 最大工作電流:35 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-80 封裝: |
| SN74ALVC7813-20DLR | 功能描述:先進(jìn)先出 64 x 18 3.3-V Synch 先進(jìn)先出 Memory RoHS:否 制造商:IDT 電路數(shù)量: 數(shù)據(jù)總線寬度:18 bit 總線定向:Unidirectional 存儲(chǔ)容量:4 Mbit 定時(shí)類型:Synchronous 組織:256 K x 18 最大時(shí)鐘頻率:100 MHz 訪問時(shí)間:10 ns 電源電壓-最大:3.6 V 電源電壓-最小:6 V 最大工作電流:35 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-80 封裝: |
| SN74ALVC7813-25DL | 功能描述:先進(jìn)先出 16-Bit Bus Trnscvr With 3-State Outputs RoHS:否 制造商:IDT 電路數(shù)量: 數(shù)據(jù)總線寬度:18 bit 總線定向:Unidirectional 存儲(chǔ)容量:4 Mbit 定時(shí)類型:Synchronous 組織:256 K x 18 最大時(shí)鐘頻率:100 MHz 訪問時(shí)間:10 ns 電源電壓-最大:3.6 V 電源電壓-最小:6 V 最大工作電流:35 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-80 封裝: |
| SN74ALVC7813-25DLR | 功能描述:先進(jìn)先出 64 x 18 3.3-V Synch 先進(jìn)先出 Memory RoHS:否 制造商:IDT 電路數(shù)量: 數(shù)據(jù)總線寬度:18 bit 總線定向:Unidirectional 存儲(chǔ)容量:4 Mbit 定時(shí)類型:Synchronous 組織:256 K x 18 最大時(shí)鐘頻率:100 MHz 訪問時(shí)間:10 ns 電源電壓-最大:3.6 V 電源電壓-最小:6 V 最大工作電流:35 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-80 封裝: |
| SN74ALVC7813-40DL | 功能描述:先進(jìn)先出 16-Bit Buffer/Driver With 3-State Outputs RoHS:否 制造商:IDT 電路數(shù)量: 數(shù)據(jù)總線寬度:18 bit 總線定向:Unidirectional 存儲(chǔ)容量:4 Mbit 定時(shí)類型:Synchronous 組織:256 K x 18 最大時(shí)鐘頻率:100 MHz 訪問時(shí)間:10 ns 電源電壓-最大:3.6 V 電源電壓-最小:6 V 最大工作電流:35 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-80 封裝: |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。