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參數(shù)資料
型號: SN74ALVCH162832DGG
廠商: Texas Instruments, Inc.
英文描述: 1-BIT TO 4-BIT ADDRESS REGISTER/DRIVER WITH 3-STATE OUTPUTS
中文描述: 1位到4位地址寄存器/驅(qū)動器,三態(tài)輸出
文件頁數(shù): 1/9頁
文件大小: 127K
代理商: SN74ALVCH162832DGG
SN74ALVCH162832
1-BIT TO 4-BIT ADDRESS REGISTER/DRIVER
WITH 3-STATE OUTPUTS
SCAS588F – MAY 1997 – REVISED JUNE 1999
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Member of the Texas Instruments
Widebus
Family
EPIC
(Enhanced-Performance Implanted
CMOS) Submicron Process
Output Ports Have Equivalent 26-
Series
Resistors, So No External Resistors Are
Required
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
Latch-Up Performance Exceeds 250 mA Per
JESD 17
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
Packaged in Thin Shrink Small-Outline
Package
NOTE: For tape and reel order entry:
The DGGR package is abbreviated to GR.
description
This 1-bit to 4-bit address register/driver is
designed for 1.65-V to 3.6-V V
CC
operation.
This device is ideal for use in applications in which
a single address bus is driving four separate
memory locations. The SN74ALVCH162832 can
be used as a buffer or a register, depending on the
logic level of the select (SEL) input.
When SEL is a logic high, the device is in the buffer
mode. The outputs follow the inputs and are
controlled by the two output-enable (OE) inputs.
Each OE controls two groups of seven outputs.
When SEL is a logic low, the device is in the
register mode. The register is an edge-triggered
D-type flip-flop. On the positive transition of the
clock (CLK) input, data at the A inputs is stored in
the internal registers. OE controls operate the
same as in the buffer mode.
When OE is a logic low, the outputs are in a normal logic state (high or low logic level). When OE is a logic high,
the outputs are in the high-impedance state.
Neither SEL nor OE affect the internal operation of the flip-flops. Old data can be retained or new data can be
entered while the outputs are in the high-impedance state.
The outputs, which are designed to sink up to 12 mA, include equivalent 26-
resistors to reduce overshoot
and undershoot.
Copyright
1999, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC and Widebus are trademarks of Texas Instruments Incorporated.
DGG PACKAGE
(TOP VIEW)
NC – No internal connection
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4Y1
3Y1
GND
2Y1
1Y1
V
CC
A1
GND
A2
GND
A3
V
CC
NC
GND
CLK
OE1
OE2
SEL
GND
A4
A5
V
CC
GND
A6
GND
A7
V
CC
4Y7
3Y7
GND
2Y7
1Y7
1Y2
2Y2
GND
3Y2
4Y2
V
CC
1Y3
2Y3
GND
3Y3
4Y3
GND
V
CC
GND
1Y4
2Y4
3Y4
4Y4
GND
1Y5
2Y5
V
CC
3Y5
4Y5
GND
GND
V
CC
1Y6
2Y6
GND
3Y6
4Y6
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SN74ALVCH162835DLR 功能描述:總線收發(fā)器 18-Bit Univ Bus Drv With 3-State Outputs RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel
SN74ALVCH162835GR 功能描述:總線收發(fā)器 18bit Univ Bus RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel
SN74ALVCH162835VR 功能描述:總線收發(fā)器 18bit Univ Bus RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel
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