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參數資料
型號: SN74ALVCH374PWRG4
廠商: TEXAS INSTRUMENTS INC
元件分類: 總線收發器
英文描述: ALVC/VCX/A SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDSO20
封裝: GREEN, PLASTIC, TSSOP-20
文件頁數: 1/15頁
文件大小: 416K
代理商: SN74ALVCH374PWRG4
www.ti.com
FEATURES
DB, DGV, DW, N, OR PW PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
OE
1Q
1D
2D
2Q
3Q
3D
4D
4Q
GND
VCC
8Q
8D
7D
7Q
6Q
6D
5D
5Q
CLK
DESCRIPTION/ORDERING INFORMATION
SN74ALVCH374
OCTAL POSITIVE EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS
SCES118G – JULY 1997 – REVISED OCTOBER 2004
Operates From 1.65 V to 3.6 V
Max tpd of 3.6 ns at 3.3 V
±24-mA Output Drive at 3.3 V
Bus Hold on Data Inputs Eliminates the Need
for External Pullup/Pulldown Resistors
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
This octal edge-triggered D-type flip-flop is designed for 1.65-V to 3.6-V VCC operation.
The SN74ALVCH374 is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers,
and working registers. On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels
at the data (D) inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or
low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the
bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines
without interface or pullup components.
OE does not affect internal operations of the latch. Old data can be retained or new data can be entered while
the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors
with the bus-hold circuitry is not recommended.
ORDERING INFORMATION
TA
PACKAGE(1)
ORDERABLE PART NUMBER
TOP-SIDE MARKING
PDIP - N
Tube
SN74ALVCH374N
Tube
SN74ALVCH374DW
SOIC - DW
ALVCH374
Tape and reel
SN74ALVCH374DWR
-40
°C to 85°C
SSOP - DB
Tape and reel
SN74ALVCH374DBR
VB374
Tube
SN74ALVCH374PW
TSSOP - PW
VB374
Tape and reel
SN74ALVCH374PWR
TVSOP - DGV
Tape and reel
SN74ALVCH374DGVR
VB374
(1)
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright 1997–2004, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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PDF描述
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相關代理商/技術參數
參數描述
SN74ALVCHG162280GR 功能描述:通用總線函數 16-To-32 Bit Reg Bus Exchanger RoHS:否 制造商:Texas Instruments 邏輯類型:CMOS 邏輯系列:74VMEH 電路數量:1 開啟電阻(最大值): 傳播延遲時間:10.1 ns 電源電壓-最大:3.45 V 電源電壓-最小:3.15 V 最大工作溫度:+ 85 C 最小工作溫度:0 C 封裝 / 箱體:TSSOP-48 封裝:Reel
SN74ALVCHG162282GR 功能描述:通用總線函數 18-Bit To 36-Bit Reg Bus Exchg W/3-St Otp RoHS:否 制造商:Texas Instruments 邏輯類型:CMOS 邏輯系列:74VMEH 電路數量:1 開啟電阻(最大值): 傳播延遲時間:10.1 ns 電源電壓-最大:3.45 V 電源電壓-最小:3.15 V 最大工作溫度:+ 85 C 最小工作溫度:0 C 封裝 / 箱體:TSSOP-48 封裝:Reel
SN74ALVCHR162245DL 功能描述:總線收發器 Tri-State 16-Bit Bus RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel
SN74ALVCHR162245DLR 制造商:Rochester Electronics LLC 功能描述:- Bulk
SN74ALVCHR162269ADLR 制造商:Texas Instruments 功能描述:
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