
SN74ALS841, SN74AS841A . . . DW OR NT PACKAGE
(TOP VIEW)
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OE
1D
2D
3D
4D
5D
6D
7D
8D
9D
10D
GND
VCC
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
9Q
10Q
LE
SN74ALS842 . . . DW OR NT PACKAGE
(TOP VIEW)
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OE
1D
2D
3D
4D
5D
6D
7D
8D
9D
10D
GND
VCC
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
9Q
10Q
LE
SN74ALS841, SN74AS841A, SN74ALS842
10-BIT BUS-INTERFACE D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SDAS059C – DECEMBER 1983 – REVISED JANUARY 1995
Copyright
1995, Texas Instruments Incorporated
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
3-State Buffer-Type Outputs Drive Bus
Lines Directly
Bus-Structured Pinout
Provide Extra Bus-Driving Latches
Necessary for Wider Address/Data Paths or
Buses With Parity
Buffered Control Inputs to Reduce
dc Loading Effects
Power-Up High-Impedance State
Package Options Include Plastic
Small-Outline (DW) Packages and Standard
Plastic (NT) 300-mil DIPs
description
These 10-bit latches feature 3-state outputs
designed specifically for driving highly capacitive
or relatively low-impedance loads. They are
particularly suitable for implementing buffer
registers, I/O ports, bidirectional bus drivers, and
working registers.
The ten latches are transparent D-type latches.
The
SN74ALS841
and
SN74AS841A
have
noninverting data (D) inputs. The SN74ALS842
has inverting D inputs.
A buffered output-enable (OE) input places the ten
outputs in either a normal logic state (high or low
logic levels) or a high-impedance state. In the
high-impedance state, the outputs neither load
nor
drive
the
bus
lines
significantly.
The
high-impedance state and increased drive provide
the capability to drive bus lines without interface or
pullup components.
OE does not affect the internal operation of the latches. Previously stored data can be retained or new data can
be entered while the outputs are off.
The SN74ALS841, SN74AS841A, and SN74ALS842 are characterized for operation from 0
°C to 70°C.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.