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參數資料
| 型號： | SN74AUP1G125YEPR |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 總線收發器 |
| 英文描述： | AUP/ULP/V SERIES, 1-BIT DRIVER, TRUE OUTPUT, BGA5 |
| 封裝： | DSBGA-5 |
| 文件頁數： | 1/17頁 |
| 文件大小： | 436K |
| 代理商： | SN74AUP1G125YEPR |
www.ti.com
FEATURES
3
2
4
5
1
OE
VCC
Y
A
GND
DBV PACKAGE
(TOP VIEW)
YEP OR YZP PACKAGE
(BOTTOM VIEW)
DCK PACKAGE
(TOP VIEW)
3
2
4
5
1
OE
VCC
Y
A
GND
3
2
4
5
1
OE
VCC
Y
A
GND
OE
GND
VCC
Y
A
DRL PACKAGE
(TOP VIEW)
See mechanical drawings for dimensions.
1
4
2
3
5
DESCRIPTION/ORDERING INFORMATION
AUP
LVC
AUP
LVC
Static-Power Consumption
(
A)
Dynamic-Power Consumption
(pF)
Single, dual, and triple gates
3.3-V
Logic
3.3-V
Logic
0%
20%
40%
60%
80%
100%
0%
20%
40%
60%
80%
100%
0.5
0
0.5
1
1.5
2
2.5
3
3.5
0
5
10
15
20
25
30
35
40
45
Time ns
V
oltage
V
AUP1G08 data at CL = 15 pF
Output
Input
Switching Characteristics
at 25 MHz
SN74AUP1G125
LOW-POWER SINGLE BUS BUFFER GATE
WITH 3-STATE OUTPUT
SCES595E – JULY 2004 – REVISED JULY 2005
Available in the Texas Instruments
Wide Operating V
CC Range of 0.8 V to 3.6 V
NanoStar and NanoFree Packages
Optimized for 3.3-V Operation
Low Static-Power Consumption
3.6-V I/O Tolerant to Support Mixed-Mode
(I
CC = 0.0 A Max)
Signal Operation
Low Dynamic-Power Consumption
t
pd = 4.6 ns Max at 3.3 V
(C
pd = 4 pF Typ at 3.3 V)
Suitable for Point-to-Point Applications
Low Input Capacitance (C
i = 1.5 pF Typ)
Latch-Up Performance Exceeds 100 mA Per
Low Noise – Overshoot and Undershoot
JESD 78, Class II
<10% of V
CC
ESD Performance Tested Per JESD 22
Input-Disable Feature Allows Floating Input
– 2000-V Humna-Body Model
Conditions
(A114-B, Class II)
I
off Supports Partial-Power-Down Mode
– 200-V Machine Model (A115-A)
Operation
– 1000-V Charged-Device Model (C101)
Input Hysteresis Allows Slow Input Transition
ESD Protection Exceeds
±5000 V With
and Better Switching Noise Immunity at Input
Human-Body Model
The AUP family is TI's premier solution to the industry's low-power needs in battery-powered portable
applications. This family ensures a very low static and dynamic power consumption across the entire VCC range
of 0.8 V to 3.6 V, resulting in an increased battery life. This product also maintains excellent signal integrity (see
Figures 1 and 2).
xxxx
Figure 1. AUP – The Lowest-Power Family
Figure 2. Excellent Signal Integrity
xxx
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoStar, NanoFree are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright 2004–2005, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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相關代理商/技術參數 |
參數描述 |
|---|---|
| SN74AUP1G125YFPR | 功能描述:緩沖器和線路驅動器 Lo-Pwr Sgl Bus Bfr Gate RoHS:否 制造商:Micrel 輸入線路數量:1 輸出線路數量:2 極性:Non-Inverting 電源電壓-最大:+/- 5.5 V 電源電壓-最小:+/- 2.37 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:MSOP-8 封裝:Reel |
| SN74AUP1G125YZPR | 功能描述:緩沖器和線路驅動器 LoPwrSngl BusBffrGt RoHS:否 制造商:Micrel 輸入線路數量:1 輸出線路數量:2 極性:Non-Inverting 電源電壓-最大:+/- 5.5 V 電源電壓-最小:+/- 2.37 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:MSOP-8 封裝:Reel |
| SN74AUP1G125YZTR | 功能描述:緩沖器和線路驅動器 Lo PWR SNGL Bus Bufr Gate RoHS:否 制造商:Micrel 輸入線路數量:1 輸出線路數量:2 極性:Non-Inverting 電源電壓-最大:+/- 5.5 V 電源電壓-最小:+/- 2.37 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:MSOP-8 封裝:Reel |
| SN74AUP1G126DBVR | 功能描述:緩沖器和線路驅動器 Lo Pwr Sngl Bus Buffer Gate RoHS:否 制造商:Micrel 輸入線路數量:1 輸出線路數量:2 極性:Non-Inverting 電源電壓-最大:+/- 5.5 V 電源電壓-最小:+/- 2.37 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:MSOP-8 封裝:Reel |
| SN74AUP1G126DBVT | 功能描述:緩沖器和線路驅動器 Lo PWR SNGL Bus Bufr Gate RoHS:否 制造商:Micrel 輸入線路數量:1 輸出線路數量:2 極性:Non-Inverting 電源電壓-最大:+/- 5.5 V 電源電壓-最小:+/- 2.37 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:MSOP-8 封裝:Reel |
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