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參數(shù)資料
| 型號： | SN74AUP2G80RSER |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 鎖存器 |
| 英文描述： | AUP/ULP/V SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, QCC8 |
| 封裝： | QFN-8 |
| 文件頁數(shù)： | 1/20頁 |
| 文件大小： | 725K |
| 代理商： | SN74AUP2G80RSER |
DCU PACKAGE
(TOP VIEW)
1
8
2
7
3
6
1CLK
1D
2Q
GND
4
5
V
CC
1Q
2D
2CLK
RSE PACKAGE
(TOP VIEW)
1
7
2
6
8
3
5
4
V
CC
1Q
2D
2CLK
GND
1CLK
1D
2Q
YFP PACKAGE
(TOP VIEW)
1 8
V
CC
2 7
1Q
3 6
2D
1CLK
1D
2Q
GND
4 5
2CLK
1
8
2
7
3
6
1CLK
1D
2Q
GND 4
5
V
CC
1Q
2D
2CLK
DQE PACKAGE
(TOP VIEW)
D1
D2
C1
C2
B1
B2
A1
A2
(A)
Single, dual, and triple gates
Static-Power Consumption
(A)
AUP
AUP
3.3-V
Logic
(A)
0%
20%
40%
60%
80%
100%
Dynamic-Power Consumption
(pF)
AUP
AUP
3.3-V
Logic
(A)
0%
20%
40%
60%
80%
100%
Switching Characteristics
at 25 MHz
(A)
-0.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
0
5
10
15
20
25
30
35
40
45
Time (ns)
V
oltage
(V)
Output
Input
(A) SN74AUP2Gxx data at C = 15 pF.
L
www.ti.com
SCES756A – DECEMBER 2009 – REVISED MARCH 2010
LOW-POWER DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP
Check for Samples: SN74AUP2G80
1
FEATURES
Available in the Texas Instruments NanoStar
Optimized for 3.3-V Operation
Package
3.6-V I/O Tolerant to Support Mixed-Mode
Low Static-Power Consumption
Signal Operation
(ICC = 0.9 mA Maximum)
tpd = 4.4 ns Maximum at 3.3 V
Low Dynamic-Power Consumption
Suitable for Point-to-Point Applications
(Cpd = 4.3 pF Typ at 3.3 V)
Latch-Up Performance Exceeds 100 mA Per
Low Input Capacitance (Ci = 1.5 pF Typical)
JESD 78, Class II
Low Noise – Overshoot and Undershoot
ESD Performance Tested Per JESD 22
<10% of VCC
–
2000-V Human-Body Model
Ioff Supports Partial-Power-Down Mode
(A114-B, Class II)
Operation
–
1000-V Charged-Device Model (C101)
Wide Operating VCC Range of 0.8 V to 3.6 V
See mechanical drawings for dimensions.
DESCRIPTION/ORDERING INFORMATION
The AUP family is TI's premier solution to the industry's low-power needs in battery-powered portable
applications. This family ensures a very low static- and dynamic-power consumption across the entire VCC range
of 0.8 V to 3.6 V, resulting in increased battery life (see Figure 1). This product also maintains excellent signal
integrity (see the very low undershoot and overshoot characteristics shown in Figure 2).
Figure 1. AUP – The Lowest-Power Family
Figure 2. Excellent Signal Integrity
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright 2009–2010, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| SN74AUP2G80YFPR | 功能描述:觸發(fā)器 Low-Pwr Dual Pos- Edge-Trgd D-Type RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel |
| SN74AUP3G04DCUR | 功能描述:緩沖器和線路驅(qū)動器 Low-Power Triple Inverter Gate RoHS:否 制造商:Micrel 輸入線路數(shù)量:1 輸出線路數(shù)量:2 極性:Non-Inverting 電源電壓-最大:+/- 5.5 V 電源電壓-最小:+/- 2.37 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:MSOP-8 封裝:Reel |
| SN74AUP3G04DCUR | 制造商:Texas Instruments 功能描述:Inverter Logic IC 制造商:Texas Instruments 功能描述:IC, TRIPLE INVERTER, US8 |
| SN74AUP3G04DQER | 功能描述:緩沖器和線路驅(qū)動器 Low-Power Triple Inverter Gate RoHS:否 制造商:Micrel 輸入線路數(shù)量:1 輸出線路數(shù)量:2 極性:Non-Inverting 電源電壓-最大:+/- 5.5 V 電源電壓-最小:+/- 2.37 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:MSOP-8 封裝:Reel |
| SN74AUP3G04RSER | 功能描述:變換器 Lo-Pwr Trpl Inverter Gate RoHS:否 制造商:NXP Semiconductors 電路數(shù)量:6 邏輯系列:74ABT 邏輯類型:BiCMOS 高電平輸出電流:- 15 mA 低電平輸出電流:20 mA 傳播延遲時間:2.2 ns 電源電壓-最大:5.5 V 電源電壓-最小:4.5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 工作溫度范圍: 封裝 / 箱體:DIP-14 封裝:Tube |
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