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Family
DOC Circuitry Dynamically Changes Output
Impedance, Resulting in Noise Reduction
Without Speed Degradation
Dynamic Drive Capability Is Equivalent to
Standard Outputs With I
OH
and I
OL
of
–
±
24 mA at 3-V V
CC
–
±
15 mA at 2.3-V V
CC
–
±
9 mA at 1.65-V V
CC
–
±
6 mA at 1.4-V V
CC
Control Inputs V
IH
/V
IL
Levels Are Referenced
to V
CCB
Voltage
If Either V
CC
Input Is at GND, Both Ports Are in
the High-Impedance State
DESCRIPTION/ORDERING INFORMATION
This 32-bit noninverting bus transceiver uses two separate configurable power-supply rails. The A port is
designed to track V
. V
accepts any supply voltage from 1.4 V to 3.6 V. The B port is designed to track
V
CCB
. V
CCB
accepts any supply voltage from 1.4 V to 3.6 V. This allows for universal low-voltage bidirectional
translation between any of the 1.5-V, 1.8-V, 2.5-V, and 3.3-V voltage nodes.
SN74AVCBH324245
32-BIT DUAL-SUPPLY BUS TRANSCEIVER
WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
SCES550B–FEBRUARY 2004–REVISED JUNE 2005
Inputs/Outputs Can Tolerate up to 4.6 V,
Which Allows Mixed-Voltage-Mode Data
Communications
I
off
Supports Partial-Power-Down Mode
Operation
Fully Configurable Dual-Rail Design Allows
Each Port to Operate Over Full 1.4-V to 3.6-V
Power-Supply Range
Bus Hold on Data Inputs Eliminates the Need
for External Pullup/Pulldown Resistors
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
The SN74AVCBH324245 is designed for asynchronous communication between data buses. The device
transmits data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the
direction-control (DIR) input. The output-enable (OE) input is used to disable the outputs, so the buses effectively
are isolated.
The SN74AVCBH324245 is designed so that the control pins (1DIR, 2DIR, 1OE, and 2OE) are supplied by V
CCB
.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. Use of pullup or
pulldown resistors with the bus-hold circuitry is not recommended.
To ensure the high-impedance state during power up or power down, OE should be tied to V
CCB
through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
This device is fully specified for partial-power-down applications using I
. The I
circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down. If either V
CC
input is at GND,
both ports are in the high-impedance state.
ORDERING INFORMATION
T
A
PACKAGE
(1)
ORDERABLE PART NUMBER
SN74AVCBH324245KR
74AVCBH324245ZKER
TOP-SIDE MARKING
LFBGA – GKE
LFBGA – ZKE
Tape and reel
Tape and reel
–40°C to 85°C
WN4245
(1)
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus+, DOC are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright 2004–2005, Texas Instruments Incorporated