- 您現在的位置：買賣IC網 > PDF目錄383820 > SN74GTLP1394DGVR Bus Exchanger PDF資料下載
參數資料
| 型號： | SN74GTLP1394DGVR |
| 英文描述： | Bus Exchanger |
| 中文描述： | 總線交換 |
| 文件頁數： | 1/16頁 |
| 文件大小： | 234K |
| 代理商： | SN74GTLP1394DGVR |
SN74GTLP1394
2-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER
WITH SPLIT LVTTL PORT FEEDBACK PATH, AND SELECTABLE POLARITY
SCES286E – OCTOBER 1999 – REVISED AUGUST 2001
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
TI-OPC
Circuitry Limits Ringing on
Unevenly Loaded Backplanes
OEC
Circuitry Improves Signal Integrity
and Reduces Electromagnetic Interference
Bidirectional Interface Between GTLP
Signal Levels and LVTTL Logic Levels
Split LVTTL Port Provides a Feedback Path
for Control and Diagnostics Monitoring
LVTTL Interfaces Are 5-V Tolerant
High-Drive GTLP Outputs (100 mA)
LVTTL Outputs (–24 mA/24 mA)
Variable Edge-Rate Control (ERC) Input
Selects GTLP Rise and Fall Times for
Optimal Data-Transfer Rate and Signal
Integrity in Distributed Loads
I
off
, Power-Up 3-State, and BIAS V
CC
Support Live Insertion
Polarity Control Selects True or
Complementary Outputs
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
description
The SN74GTLP1394 is a high-drive, 2-bit, 3-wire bus transceiver that provides LVTTL-to-GTLP and
GTLP-to-LVTTL signal-level translation. It allows for transparent and inverted transparent modes of data
transfer with separate LVTTL input and LVTTL output pins, which provides a feedback path for control and
diagnostics monitoring. The device provides a high-speed interface between cards operating at LVTTL logic
levels and a backplane operating at GTLP signal levels, and is especially designed to work with the
Texas Instruments 1394 backplane physical-layer controllers. High-speed (about three times faster than
standard LVTTL or TTL) backplane operation is a direct result of GTLP reduced output swing (<1 V), reduced
input threshold levels, improved differential input, OEC
circuitry, and TI-OPC
circuitry. Improved GTLP OEC
and TI-OPC circuitry minimizes bus-settling time and have been designed and tested using several backplane
models. The high drive allows incident-wave switching in heavily loaded backplanes with equivalent load
impedance down to 11
.
GTLP is the Texas Instruments (TI
) derivative of the Gunning Transceiver Logic (GTL) JEDEC standard
JESD 8-3. The ac specification of the SN74GTLP1394 is given only at the preferred higher noise margin GTLP,
but the user has the flexibility of using this device at either GTL (V
TT
= 1.2 V and V
REF
= 0.8 V) or GTLP
(V
TT
= 1.5 V and V
REF
= 1 V) signal levels.
Normally, the B port operates at GTLP signal levels. The A-port and control inputs operate at LVTTL logic levels,
but are 5-V tolerant and are compatible with TTL and 5-V CMOS inputs. V
REF
is the B port differential input
reference voltage.
Copyright
2001, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
D, DGV, OR PW PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
OEBY
Y1
Y2
V
CC
A1
A2
OEAB
ERC
BIAS V
CC
GND
B1
GND
B2
GND
V
REF
T/C
OEC, TI, and TI-OPC are trademarks of Texas Instruments.
相關PDF資料 |
PDF描述 |
|---|---|
| SN74GTLP1394DR | Bus Exchanger |
| SN74GTLP1394PWR | Bus Exchanger |
| SN74HC4515DW | 4-To-16-Line Demultiplexer |
| CD74HC10H | Triple 3-input NAND Gate |
| CD74HC112NSR96 | FLIP-FLOP|DUAL|J/K TYPE|HC-CMOS|SOP|16PIN|PLASTIC |
相關代理商/技術參數 |
參數描述 |
|---|---|
| SN74GTLP1394DR | 功能描述:轉換 - 電壓電平 2bit Bus RoHS:否 制造商:Micrel 類型:CML/LVDS/LVPECL to LVCMOS/LVTTL 傳播延遲時間:1.9 ns 電源電流:14 mA 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:MLF-8 |
| SN74GTLP1394DRE4 | 功能描述:轉換 - 電壓電平 2-Bit LVTTL/GTLP Bus Xcvr Adj-Edge-Rate RoHS:否 制造商:Micrel 類型:CML/LVDS/LVPECL to LVCMOS/LVTTL 傳播延遲時間:1.9 ns 電源電流:14 mA 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:MLF-8 |
| SN74GTLP1394DRG4 | 功能描述:轉換 - 電壓電平 2B LVTTL to GTLP Adj Edg RateBus Xcvr RoHS:否 制造商:Micrel 類型:CML/LVDS/LVPECL to LVCMOS/LVTTL 傳播延遲時間:1.9 ns 電源電流:14 mA 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:MLF-8 |
| SN74GTLP1394PW | 功能描述:轉換 - 電壓電平 2-Bit LVTTL/GTLP Bus Xcvr Adj-Edge-Rate RoHS:否 制造商:Micrel 類型:CML/LVDS/LVPECL to LVCMOS/LVTTL 傳播延遲時間:1.9 ns 電源電流:14 mA 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:MLF-8 |
| SN74GTLP1394PWE4 | 功能描述:轉換 - 電壓電平 2-Bit LVTTL/GTLP Bus Xcvr Adj-Edge-Rate RoHS:否 制造商:Micrel 類型:CML/LVDS/LVPECL to LVCMOS/LVTTL 傳播延遲時間:1.9 ns 電源電流:14 mA 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:MLF-8 |
發布緊急采購，3分鐘左右您將得到回復。