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參數(shù)資料
| 型號： | SN74GTLP817DGV |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 總線收發(fā)器 |
| 英文描述： | GTLP SERIES, 6-BIT DRIVER, INVERTED OUTPUT, PDSO24 |
| 封裝： | TVSOP-24 |
| 文件頁數(shù)： | 1/11頁 |
| 文件大小： | 149K |
| 代理商： | SN74GTLP817DGV |
SN74GTLP817
GTL+-TO-LVTTL 1-TO-6 FANOUT DRIVER
SCES285A – OCTOBER 1999 – REVISED DECEMBER 1999
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D Bidirectional Interface Between GTL+
Signal Levels and LVTTL Logic Levels
D GTL+-to-LVTTL 1-to-6 Fanout Driver
D LVTTL-to-GTL+ 1-to-2 Fanout Driver
D LVTTL Interfaces Are 5-V Tolerant
D Medium-Drive GTL+ Outputs (50 mA)
D Reduced-Drive LVTTL Outputs
(–12 mA/12 mA)
D Variable Edge-Rate Control (ERC) Input
Selects GTL+ Rise and Fall Times for
Optimal Data-Transfer Rate and Signal
Integrity
D Ioff and Power-Up 3-State Support Hot
Insertion
D Distributed GND-Pin Configuration
Minimizes High-Speed Switching Noise
D Package Options Include Plastic
Small-Outline (DW), Thin Very
Small-Outline (DGV), and Thin Shrink
Small-Outline (PW) Packages
description
The SN74GTLP817 is a low-drive fanout driver that provides LVTTL-to-GTL+ and GTL+-to-LVTTL signal-level
translation. The device provides a high-speed interface between cards operating at LVTTL logic levels and a
backplane operating at GTL+ signal levels. High-speed (about two times faster than standard TTL or LVTTL)
backplane operation is a direct result of GTLP’s reduced output swing (<1 V), reduced input threshold levels,
improved differential input, and output edge control (OEC
). Improved GTLP OEC circuits minimize bus settling
time and have been designed and tested using several backplane models. The medium drive is suitable for
driving double-terminated backplanes.
GTL+ is the Texas Instruments derivative of the Gunning transceiver logic (GTL) JEDEC standard JESD 8-3.
The AC specification of the SN74GTLP817 is given only at the preferred higher noise margin GTL+, but the user
has the flexibility of using this device at either GTL (VTT = 1.2 V and VREF = 0.8 V) or GTL+ (VTT = 1.5 V and
VREF = 1 V) signal levels.
Normally, the B port operates at GTL or GTL+ levels, while the A-port and control inputs are compatible with
LVTTL logic levels and are 5-V tolerant. VREF is the reference input voltage for the B port.
GNDT is the TTL output ground, while GNDG is the GTL+ output ground, and both should be separated from
each other for a quieter device.
This device is fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry
disables the outputs, preventing damaging current backflow through the device when it is powered down. The
power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,
which prevents driver conflict.
PRODUCT
PREVIEW
Copyright
1999, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
DGV, DW, OR PW PACKAGE
(TOP VIEW)
AI
AO1
GNDT
AO2
VCC
AO3
GNDT
AO4
VCC
AO5
GNDT
AO6
GNDT
OEAB
BO1
GNDG
VREF
GNDG
ERC
BO2
GNDG
BI
OEBA
GNDT
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
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13
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
OEC is a trademark of Texas Instruments Incorporated.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SN74GTLP817DWR | GTLP SERIES, 1-BIT DRIVER, INVERTED OUTPUT, PDSO24 |
| SN74GTLP817DGVR | GTLP SERIES, 1-BIT DRIVER, INVERTED OUTPUT, PDSO24 |
| SN74GTLP817PWRG4 | GTLP SERIES, 1-BIT DRIVER, INVERTED OUTPUT, PDSO24 |
| SN74GTLP817PWG4 | GTLP SERIES, 1-BIT DRIVER, INVERTED OUTPUT, PDSO24 |
| SN74GTLP817DW | GTLP SERIES, 1-BIT DRIVER, INVERTED OUTPUT, PDSO24 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SN74GTLP817DGVR | 功能描述:轉(zhuǎn)換 - 電壓電平 1 to 6 GTLP-LVTTL RoHS:否 制造商:Micrel 類型:CML/LVDS/LVPECL to LVCMOS/LVTTL 傳播延遲時間:1.9 ns 電源電流:14 mA 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:MLF-8 |
| SN74GTLP817DGVRE4 | 功能描述:轉(zhuǎn)換 - 電壓電平 Octal Buffer/Driver With 3-State Outputs RoHS:否 制造商:Micrel 類型:CML/LVDS/LVPECL to LVCMOS/LVTTL 傳播延遲時間:1.9 ns 電源電流:14 mA 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:MLF-8 |
| SN74GTLP817DGVRG4 | 功能描述:特定功能邏輯 GTLP to LVTTL 1 to 6 Fanout Driver RoHS:否 制造商:Texas Instruments 產(chǎn)品: 系列:SN74ABTH18502A 工作電源電壓:5 V 封裝 / 箱體:LQFP-64 封裝:Tube |
| SN74GTLP817DW | 功能描述:特定功能邏輯 GTLP-to-LVTTL 1-to-6 Fanout Driver RoHS:否 制造商:Texas Instruments 產(chǎn)品: 系列:SN74ABTH18502A 工作電源電壓:5 V 封裝 / 箱體:LQFP-64 封裝:Tube |
| SN74GTLP817DWE4 | 功能描述:特定功能邏輯 GTLP-to-LVTTL 1-to-6 Fanout Driver RoHS:否 制造商:Texas Instruments 產(chǎn)品: 系列:SN74ABTH18502A 工作電源電壓:5 V 封裝 / 箱體:LQFP-64 封裝:Tube |
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