- 您現在的位置：買賣IC網 > PDF目錄374868 > SN74LS193N (ON SEMICONDUCTOR) Single Voltage E-pHEMT Low Noise +40 dBm OIP3 in SOT-89 package PDF資料下載
參數資料
| 型號： | SN74LS193N |
| 廠商： | ON SEMICONDUCTOR |
| 元件分類： | 通用總線功能 |
| 英文描述： | Single Voltage E-pHEMT Low Noise +40 dBm OIP3 in SOT-89 package |
| 中文描述： | LS SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT BIDIRECTIONAL BINARY COUNTER, PDIP16 |
| 封裝： | PLASTIC, DIP-16 |
| 文件頁數： | 1/7頁 |
| 文件大小： | 110K |
| 代理商： | SN74LS193N |
5-1
FAST AND LS TTL DATA
PRESETTABLE BCD/DECADE
UP/DOWN COUNTER
PRESETTABLE 4-BIT BINARY
UP/DOWN COUNTER
The SN54/74LS192 is an UP/DOWN BCD Decade (8421) Counter and the
SN54/74LS193 is an UP/DOWN MODULO-16 Binary Counter. Separate
Count Up and Count Down Clocks are used and in either counting mode the
circuits operate synchronously. The outputs change state synchronous with
the LOW-to-HIGH transitions on the clock inputs.
Separate Terminal Count Up and Terminal Count Down outputs are
provided which are used as the clocks for a subsequent stages without extra
logic, thus simplifying multistage counter designs. Individual preset inputs
allow the circuits to be used as programmable counters. Both the Parallel
Load (PL) and the Master Reset (MR) inputs asynchronously override the
clocks.
Low Power . . . 95 mW Typical Dissipation
High Speed . . . 40 MHz Typical Count Frequency
Synchronous Counting
Asynchronous Master Reset and Parallel Load
Individual Preset Inputs
Cascading Circuitry Internally Provided
Input Clamp Diodes Limit High Speed Termination Effects
NOTE:
The Flatpak version
has the same pinouts
(Connection Diagram) as
the Dual In-Line Package.
CONNECTION DIAGRAM DIP
(TOP VIEW)
MR
TCD
14
13
12
11
10
9
1
2
3
4
5
6
7
16
15
8
VCC
P1
P0
TCU
P2
PL
P3
Q1
Q0
CPD
CPU
Q2
Q3
GND
PIN NAMES
LOADING
(Note a)
HIGH
LOW
CPU
CPD
MR
PL
Pn
Qn
TCD
TCU
NOTES:
a. 1 TTL Unit Load (U.L.) = 40
μ
A HIGH/1.6 mA LOW.
b. The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74)
b.
Temperature Ranges.
Count Up Clock Pulse Input
Count Down Clock Pulse Input
Asynchronous Master Reset (Clear) Input
Asynchronous Parallel Load (Active LOW) Input
Parallel Data Inputs
Flip-Flop Outputs (Note b)
Terminal Count Down (Borrow) Output (Note b)
Terminal Count Up (Carry) Output (Note b)
0.5 U.L.
0.5 U.L.
0.5 U.L.
0.5 U.L.
0.5 U.L.
10 U.L.
10 U.L.
10 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
5 (2.5) U.L.
5 (2.5) U.L.
5 (2.5) U.L.
SN54/74LS192
SN54/74LS193
PRESETTABLE BCD/DECADE
UP/DOWN COUNTER
PRESETTABLE 4-BIT BINARY
UP/DOWN COUNTER
LOW POWER SCHOTTKY
J SUFFIX
CERAMIC
CASE 620-09
N SUFFIX
PLASTIC
CASE 648-08
16
1
16
1
ORDERING INFORMATION
SN54LSXXXJ
SN74LSXXXN
SN74LSXXXD
Ceramic
Plastic
SOIC
16
1
D SUFFIX
SOIC
CASE 751B-03
LOGIC SYMBOL
VCC = PIN 16
GND = PIN 8
5
4
3
2
6
7
12
9
10
1
15
11
CPD
Q0Q1
Q2 Q3
TCD
P3
P2
P1
P0
PL
CPU
TCU
13
MR
14
相關PDF資料 |
PDF描述 |
|---|---|
| SN54LS192J | PRESETTABLE BCD/DECADE UP/DOWN COUNTER PRESETTABLE 4-BIT BINARY UP/DOWN COUNTER |
| SN54LS193J | PRESETTABLE BCD/DECADE UP/DOWN COUNTER PRESETTABLE 4-BIT BINARY UP/DOWN COUNTER |
| SN74LS192D | PRESETTABLE BCD/DECADE UP/DOWN COUNTER PRESETTABLE 4-BIT BINARY UP/DOWN COUNTER |
| SN74LS192N | PRESETTABLE BCD/DECADE UP/DOWN COUNTER PRESETTABLE 4-BIT BINARY UP/DOWN COUNTER |
| SN74LS193 | PRESETTABLE BCD/DECADE UP/DOWN COUNTER PRESETTABLE 4-BIT BINARY UP/DOWN COUNTER |
相關代理商/技術參數 |
參數描述 |
|---|---|
| SN74LS193N DC90 | 制造商:Motorola 功能描述:74LS193 |
| SN74LS193N | 制造商:Texas Instruments 功能描述:IC 74LS 74LS193 DIP16 5.25V |
| SN74LS193N | 制造商:Texas Instruments 功能描述:IC 74LS 74LS193 DIP16 5.25V |
| SN74LS193N | 制造商:Texas Instruments 功能描述:Counter / Multiplier / Divider Logic IC |
| SN74LS193N3 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
發布緊急采購，3分鐘左右您將得到回復。