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參數資料
| 型號： | SN74LV573ADBLE |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 總線收發器 |
| 英文描述： | LV/LV-A/LVX/H SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDSO20 |
| 封裝： | PLASTIC, SSOP-20 |
| 文件頁數： | 1/12頁 |
| 文件大小： | 209K |
| 代理商： | SN74LV573ADBLE |
SN54LV573A, SN74LV573A
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCLS411C – APRIL 1998 – REVISED MAY 2000
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D EPIC (Enhanced-Performance Implanted
CMOS) Process
D Typical VOLP (Output Ground Bounce)
<0.8 V at VCC = 3.3 V , TA = 25°C
D Typical VOHV (Output VOH Undershoot)
>2.3 V at VCC = 3.3 V , TA = 25°C
D 2-V to 5.5-V VCC Operation
D Support Mixed-Mode Voltage Operation on
All Ports
D Latch-Up Performance Exceeds 250 mA Per
JESD 17
D ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
D Package Options Include Plastic
Small-Outline (DW, NS), Shrink
Small-Outline (DB), Thin Very Small-Outline
(DGV), and Thin Shrink Small-Outline (PW)
Packages, Ceramic Flat (W) Packages, Chip
Carriers (FK), and DIPs (J)
description
The ’LV573A devices are octal transparent D-type
latches designed for 2-V to 5.5-V VCC operation.
These devices feature 3-state outputs designed
specifically for driving highly capacitive or
relatively low-impedance loads. This device is
particularly suitable for implementing buffer
registers, I/O ports, bidirectional bus drivers, and
working registers.
While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the
Q outputs are latched at the logic levels set up at the D inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high
or low logic levels) or high-impedance state. In the high-impedance state, the outputs neither load nor drive the
bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines
without need for interface or pullup components.
OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN54LV573A is characterized for operation over the full military temperature range of –55
°C to 125°C.
The SN74LV573A is characterized for operation from –40
°C to 85°C.
Copyright
2000, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
EPIC is a trademark of Texas Instruments.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SN54LV573A . . . FK PACKAGE
(TOP VIEW)
SN54LV573A ...J OR W PACKAGE
SN74LV573A . . . DB, DGV, DW, NS, OR PW PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
OE
1D
2D
3D
4D
5D
6D
7D
8D
GND
VCC
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
LE
32
1 20 19
910 11 12 13
4
5
6
7
8
18
17
16
15
14
2Q
3Q
4Q
5Q
6Q
3D
4D
5D
6D
7D
2D
1D
OE
8Q
7Q
1Q
8D
GND
LE
V
CC
相關PDF資料 |
PDF描述 |
|---|---|
| SN74LV573APWRE4 | LV/LV-A/LVX/H SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDSO20 |
| SN74LV573AGQNR | LV/LV-A/LVX/H SERIES, 8-BIT DRIVER, TRUE OUTPUT, PBGA20 |
| SN74LV573ADBR | LV/LV-A/LVX/H SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDSO20 |
| SNJ54LV573AJ | LV/LV-A/LVX/H SERIES, 8-BIT DRIVER, TRUE OUTPUT, CDIP20 |
| SN74LV573ATDGVRG4 | LV/LV-A/LVX/H SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDSO20 |
相關代理商/技術參數 |
參數描述 |
|---|---|
| SN74LV573ADBR | 功能描述:閉鎖 Tri-St Octal D-Type RoHS:否 制造商:Micrel 電路數量:1 邏輯類型:CMOS 邏輯系列:TTL 極性:Non-Inverting 輸出線路數量:9 高電平輸出電流: 低電平輸出電流: 傳播延遲時間: 電源電壓-最大:12 V 電源電壓-最小:5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-16 封裝:Reel |
| SN74LV573ADBRE4 | 功能描述:閉鎖 Tri-St Octal D-Type RoHS:否 制造商:Micrel 電路數量:1 邏輯類型:CMOS 邏輯系列:TTL 極性:Non-Inverting 輸出線路數量:9 高電平輸出電流: 低電平輸出電流: 傳播延遲時間: 電源電壓-最大:12 V 電源電壓-最小:5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-16 封裝:Reel |
| SN74LV573ADBRG4 | 功能描述:閉鎖 Octal Transp DType 閉鎖 RoHS:否 制造商:Micrel 電路數量:1 邏輯類型:CMOS 邏輯系列:TTL 極性:Non-Inverting 輸出線路數量:9 高電平輸出電流: 低電平輸出電流: 傳播延遲時間: 電源電壓-最大:12 V 電源電壓-最小:5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-16 封裝:Reel |
| SN74LV573ADGVR | 功能描述:閉鎖 Octal Transp DType 閉鎖 RoHS:否 制造商:Micrel 電路數量:1 邏輯類型:CMOS 邏輯系列:TTL 極性:Non-Inverting 輸出線路數量:9 高電平輸出電流: 低電平輸出電流: 傳播延遲時間: 電源電壓-最大:12 V 電源電壓-最小:5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-16 封裝:Reel |
| SN74LV573ADGVRE4 | 功能描述:閉鎖 Octal Transp DType 閉鎖 RoHS:否 制造商:Micrel 電路數量:1 邏輯類型:CMOS 邏輯系列:TTL 極性:Non-Inverting 輸出線路數量:9 高電平輸出電流: 低電平輸出電流: 傳播延遲時間: 電源電壓-最大:12 V 電源電壓-最小:5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-16 封裝:Reel |
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