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參數資料
型號: SN74LVC1G74DCUR
廠商: TEXAS INSTRUMENTS INC
元件分類: 鎖存器
英文描述: D FLIP-FLOP, PDSO8
封裝: GREEN, PLASTIC, US8,8-PINS
文件頁數: 1/16頁
文件大小: 619K
代理商: SN74LVC1G74DCUR
1
FEATURES
See mechanical drawings for dimensions.
DCT PACKAGE
(TOP VIEW)
1
V
CC
8
CLK
2
7
D
PRE
3
6
Q
CLR
4
5
GND
Q
DCU PACKAGE
(TOP VIEW)
3
6
CLR
Q
8
1
V
CC
CLK
5
GND
4
Q
2
7
PRE
D
CLK
D
GND
Q
V
CC
PRE
CLR
Q
YZP PACKAGE
(TOP VIEW)
4 5
3 6
2 7
1 8
A1
A2
B1
B2
C1
C2
D1
D2
DESCRIPTION/ORDERING INFORMATION
www.ti.com ............................................................................................................................................................................................. SCES794 – OCTOBER 2009
SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH CLEAR AND PRESET
2
Available in the Texas Instruments NanoFree
Typical V
OHV (Output VOH Undershoot)
Package
>2 V at VCC = 3.3 V, TA = 25°C
Supports 5-V V
CC Operation
I
off Supports Partial-Power-Down Mode
Operation
Inputs Accept Voltages to 5.5 V
Latch-Up Performance Exceeds 100 mA Per
Max t
pd of 5.9 ns at 3.3 V
JESD 78, Class II
Low Power Consumption, 10-A Max I
CC
ESD Protection Exceeds JESD 22
±24-mA Output Drive at 3.3 V
2000-V Human-Body Model (A114-A)
Typical V
OLP (Output Ground Bounce)
1000-V Charged-Device Model (C101)
<0.8 V at VCC = 3.3 V, TA = 25°C
This single positive-edge-triggered D-type flip-flop is designed for 1.65-V to 5.5-V VCC operation.
NanoFree package technology is a major breakthrough in IC packaging concepts, using the die as the
package.
A low level at the preset (PRE) or clear (CLR) input sets or resets the outputs, regardless of the levels of the
other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time
requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs
at a voltage level and is not related directly to the rise time of the clock pulse. Following the hold-time interval,
data at the D input can be changed without affecting the levels at the outputs.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
NanoFree is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright 2009, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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相關代理商/技術參數
參數描述
SN74LVC1G74DCUR 制造商:Texas Instruments 功能描述:IC, LOGIC, FLIP FLOP, D, 5.9NS, VSSOP-8
SN74LVC1G74DCURG4 功能描述:觸發(fā)器 Sgl Pos-Edge-Trgr D-Type Flip-Flop RoHS:否 制造商:Texas Instruments 電路數量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel
SN74LVC1G74DCUT 功能描述:觸發(fā)器 Sgl Pos-Edge-Trggrd RoHS:否 制造商:Texas Instruments 電路數量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel
SN74LVC1G74DQER 功能描述:觸發(fā)器 Sgl Positive-Edge Triggered Flip-Flop RoHS:否 制造商:Texas Instruments 電路數量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel
SN74LVC1G74RSE2 功能描述:觸發(fā)器 Sgl Positive-Edge Triggered Flip-Flop RoHS:否 制造商:Texas Instruments 電路數量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel
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