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參數資料
| 型號： | SN74SSTL16857DGG |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 14-BIT SSTL_2 REGISTERED BUFFER |
| 中文描述： | 14位SSTL_2注冊緩沖區 |
| 文件頁數： | 1/7頁 |
| 文件大小： | 93K |
| 代理商： | SN74SSTL16857DGG |
SN74SSTL16857
14-BIT SSTL_2 REGISTERED BUFFER
SCAS625C – FEBRUARY 1999 – REVISED OCTOBER 1999
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Member of the Texas Instruments
Widebus
Family
Supports SSTL_2 Signal Data Inputs and
Outputs
Supports LVTTL Switching Levels on the
RESET Pin
Differential CLK Signal
Flow-Through Architecture Optimizes PCB
Layout
Meets SSTL_2 Class II Specifications
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
Packaged in Plastic Thin Shrink
Small-Outline Package
description
This 14-bit registered buffer is designed for 2.3-V
to 3.6-V V
CC
operation and SSTL_2 data input
and output levels.
All inputs are compatible with the JEDEC
Standard for SSTL_2, except the LVCMOS reset
(RESET) input. All outputs are SSTL_2, Class II
compatible.
When RESET is low, the differential input receivers are disabled, and undriven (floating) data and clock inputs
are allowed. In addition, when RESET is low, all registers are reset, and all outputs are forced low. The LVCMOS
RESET input must always be held at a valid logic high or low level.
To ensure defined outputs from the register before a stable clock has been supplied, RESET must be held in
the low state during power up.
The SN74SSTL16857 is characterized for operation from 0
°
C to 70
°
C.
FUNCTION TABLE
(each flip-flop)
INPUTS
CLK
OUTPUT
Q
RESET
CLK
D
L
X
X
X
L
H
↓
↓
↑
↑
H
H
H
L
L
H
L or H
L or H
X
Q0
Copyright
1999, Texas Instruments Incorporated
Widebus is a trademark of Texas Instruments Incorporated.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
DGG PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
Q1
Q2
GND
V
DDQ
Q3
Q4
Q5
GND
V
DDQ
Q6
Q7
V
DDQ
GND
Q8
Q9
V
DDQ
GND
Q10
Q11
Q12
V
DDQ
GND
Q13
Q14
D1
D2
GND
V
CC
D3
D4
D5
D6
D7
CLK
CLK
V
CC
GND
V
REF
RESET
D8
D9
D10
D11
D12
V
CC
GND
D13
D14
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相關代理商/技術參數 |
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|---|---|
| SN74SSTL16857DGGR | 功能描述:寄存器 Single-Supply Voltage Translator RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數量:1 最大時鐘頻率:36 MHz 傳播延遲時間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube |
| SN74SSTU32864CGKER | 功能描述:寄存器 25-Bit Configurable Registered Buffer RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數量:1 最大時鐘頻率:36 MHz 傳播延遲時間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube |
| SN74SSTU32864CZKER | 功能描述:緩沖器和線路驅動器 25-Bit Configurable Registered Buffer RoHS:否 制造商:Micrel 輸入線路數量:1 輸出線路數量:2 極性:Non-Inverting 電源電壓-最大:+/- 5.5 V 電源電壓-最小:+/- 2.37 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:MSOP-8 封裝:Reel |
| SN74SSTU32864DGKER | 功能描述:緩沖器和線路驅動器 25-Bit Configurable Registered Buffer RoHS:否 制造商:Micrel 輸入線路數量:1 輸出線路數量:2 極性:Non-Inverting 電源電壓-最大:+/- 5.5 V 電源電壓-最小:+/- 2.37 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:MSOP-8 封裝:Reel |
| SN74SSTU32864DZKER | 功能描述:緩沖器和線路驅動器 25-Bit Configurable Registered Buffer RoHS:否 制造商:Micrel 輸入線路數量:1 輸出線路數量:2 極性:Non-Inverting 電源電壓-最大:+/- 5.5 V 電源電壓-最小:+/- 2.37 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:MSOP-8 封裝:Reel |
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