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參數資料
| 型號： | SNJ54HC109FK |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 鎖存器 |
| 英文描述： | HC/UH SERIES, DUAL POSITIVE EDGE TRIGGERED J-KBAR FLIP-FLOP, COMPLEMENTARY OUTPUT, CQCC20 |
| 封裝： | CERAMIC, LCC-20 |
| 文件頁數： | 1/18頁 |
| 文件大小： | 707K |
| 代理商： | SNJ54HC109FK |
SN54HC109, SN74HC109
DUAL JK POSITIVEEDGETRIGGERED
FLIPFLOPS WITH CLEAR AND PRESET
SCLS470A MARCH 2003 REVISED OCTOBER 2003
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D Wide Operating Voltage Range of 2 V to 6 V
D Low Input Current of 1 A Max
D High-Current Outputs Drive Up To
10 LSTTL Loads
D Low Power Consumption, 40-A Max ICC
D Typical tpd = 12 ns
D ±4-mA Output Drive at 5 V
SN54HC109 ...J OR W PACKAGE
SN74HC109 . . . D, N, OR NS PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1CLR
1J
1K
1CLK
1PRE
1Q
GND
VCC
2CLR
2J
2K
2CLK
2PRE
2Q
SN54HC109 . . . FK PACKAGE
(TOP VIEW)
NC No internal connection
32 1 20 19
910 11 12 13
4
5
6
7
8
18
17
16
15
14
2J
2K
NC
2CLK
2PRE
1K
1CLK
NC
1PRE
1Q
1J
1CLR
NC
2Q
V
2CLR
1Q
GND
NC
CC
description/ordering information
These devices contain two independent J-K positive-edge-triggered flip-flops. A low level at the preset (PRE)
or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR
are inactive (high), data at the J and K inputs meeting the setup-time requirements are transferred to the outputs
on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not related
directly to the rise time of the clock pulse. Following the hold-time interval, data at the J and K inputs can be
changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops by
grounding K and tying J high. They also can perform as D-type flip-flops if J and K are tied together.
ORDERING INFORMATION
TA
PACKAGE
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
PDIP N
Tube of 25
SN74HC109N
Tube of 40
SN74HC109D
40
°C to 85°C
SOIC D
Reel of 2500
SN74HC109DR
HC109
40 C to 85 C
SOIC D
Reel of 250
SN74HC109DT
HC109
SOP NS
Reel of 2000
SN74HC109NSR
HC109
CDIP J
Tube of 25
SNJ54HC109J
55
°C to 125°C
CFP W
Tube of 150
SNJ54HC109W
55 C to 125 C
LCCC FK
Tube of 55
SNJ54HC109FK
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Copyright
2003, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
On products compliant to MILPRF38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
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| SN74HC112D | HC/UH SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16 |
| SN74HC11PWTE4 | HC/UH SERIES, TRIPLE 3-INPUT AND GATE, PDSO14 |
| SNJ54HC11FKR | HC/UH SERIES, TRIPLE 3-INPUT AND GATE, CQCC20 |
相關代理商/技術參數 |
參數描述 |
|---|---|
| SNJ54HC109J | 制造商:Texas Instruments 功能描述:Flip Flop JK# -Type Pos-Edge 2-Element 16-Pin CDIP Tube |
| SNJ54HC109W | 制造商:Texas Instruments 功能描述:Flip Flop JK# -Type Pos-Edge 2-Element 16-Pin CFPAK Tube |
| SNJ54HC10FK | 制造商:Texas Instruments 功能描述:NAND Gate 3-Element 3-IN CMOS 20-Pin LCCC Tube |
| SNJ54HC10J | 制造商:Texas Instruments 功能描述:NAND Gate 3-Element 3-IN CMOS 14-Pin CDIP Tube 制造商:Rochester Electronics LLC 功能描述:8403801CA, TRIPLE 3-IN POS-NAND GATE - Bulk |
| SNJ54HC112FK | 制造商:Texas Instruments 功能描述: |
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