
Description
The SP5730 is a single chip frequency synthesiser
designed for tuning systems up to 1·3GHz and is
optimised for digital terrestrial applications. The RF
preamplifier interfaces direct with the RF programmable
divider, which is of MN1A construction so giving a step
size equal to the loop comparison frequency and no
Features
Complete 1·3 GHz Single Chip System for Digital
Terrestrial Television Applications
Selectable Reference Division Ratio, Compatible with
DTT Requirements
Optimised for Low Phase Noise, with Comparison
Frequencies up to 4 MHz
No RF Prescaler
Selectable Reference/Comparison Frequency Output
Four Selectable I
2
C Addresses
I
2
C Fast Mode Compliant with 3·3V and 5V Logic
Levels
Four Switching Ports
Functional Replacement for SP5659 (except ADC)
Pin Compatible with SP5655
Power Consumption 120mW with V
CC
= 5·5V, all Ports off
ESD Protection 2kV min., MIL-STD-883B Method 3015
Cat.1 (Normal ESD handling procedures should be
observed)
Applications
Digital Satellite, Cable and Terrestrial Tuning Systems
Communications Systems
prescaler phase noise degradation over the full RF
operating range. The comparison frequency is obtained
either from an on-chip crystal controlled oscillator, or from
an external source. The oscillator frequency, f
REF
, or phase
comparator frequency, f
COMP
, can be switched to the REF/
COMP output providing a reference for a second
frequency synthesiser. The synthesiser is controlled via
an 1
2
C bus and is fast mode compliant. It can be hard
wired to respond to one of four addresses to enable two
or more synthesisers to be used on a common bus. The
device contains four switching ports P0 - P3.
SP5730
1.3
GHz Low Phase Noise Frequency Synthesiser
Data
S
heet
November 2004
Figure 1 - SP5730 block diagram
4-BIT LATCH AND
PORT INTERFACE
4
8/9
3-BIT
COUNT
12-BIT
COUNT
15-BIT LATCH
REFERENCE
DIVIDER
REF/COMP
CRYSTAL CAP
CRYSTAL
CHARGE PUMP
DRIVE
I
2
C BUS
TRANSCEIVER
ADDRESS
SDA
SCL
RF
INPUT
P3
11
2
3
1
16
6
13
14
10
4
5
PUMP
2 BIT
5 BIT
2 BIT
2 BIT
7
8
9
P2
P1
P0
CP MODE
LOCK
f
PD
/2
f
PD
/2 SELECT
ENABLE/
SELECT
DISABLE
Absolute Maximum Ratings
All voltages are referred to V
EE
= 0V
Supply voltage, V
CC
RF differential input voltage
All I/O port DC offsets
SDA and SCL DC offset
Storage temperature
Junction temperature
QP16 thermal resistance
Chip to ambient,
θ
JA
Chip to case,
θ
JC
-0·3V to +7V
2·5Vp-p
-0·3 to V
CC
+0·3V
-0·3 to 6V
-55
°
C to +150
°
C
+150
°
C
80
°
C/W
20
°
C/W
Ordering Information
16 Pin QSOP
16 Pin QSOP
16 Pin SOIC
16 Pin SOIC*
16 Pin QSOP* Tape & Reel
SP5730A/KG/MP1T
16 Pin SOIC
SP5730A/KG/MP2T
16 Pin SOIC*
SP5730A/KG/QP2S
16 Pin QSOP* Tubes
*Pb Free Matte Tin
SP5730A/KG/QP1T
SP5730A/KG/QP1S
SP5730A/KG/MP1S
SP5730A/KG/MP2S
SP5730A/KG/QP2T
Tape & Reel
Tubes
Tubes
Tubes
Tape & Reel
Tape & Reel
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2001-2004, Zarlink Semiconductor Inc. All Rights Reserved.