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參數(shù)資料
型號(hào): SSI32F8030
廠商: Electronic Theatre Controls, Inc.
英文描述: Programmable Electronic Filter
中文描述: 可編程電子過(guò)濾器
文件頁(yè)數(shù): 1/10頁(yè)
文件大小: 76K
代理商: SSI32F8030
April 1995
DESCRIPTION
The SSI 32F8030 Programmable Electronic Filter pro-
vides an electronically controlled low–pass filter with a
separate differentiated low–pass output. A seven–
pole, 0.05
°
Equiripple-type linear phase, low–pass
filter is provided along with a single-pole, single-zero
differentiator. Both outputs have matched delays. The
delay matching is unaffected by any amount of pro-
grammed high frequency peaking (boost) or band-
width. This programability, combined with low group
delay variation makes the SSI 32F8030 ideal for use in
many applications. Double differentiation high fre-
quency boost is accomplished by a two–pole, low–
pass with a two–pole, high–pass feed forward section
to provide complementary real axis zeros. A variable
attenuator is used to program the zero locations, which
controls the amount of boost.
The SSI 32F8030 programmable boost and bandwidth
characteristics can be controlled by external DACs or
DACs provided in the SSI 32D4661 Time Base Gen-
erator. Fixed characteristics are easily accomplished
with three external resistors. In addition, boost can be
switched in or out by a logic signal.
The SSI 32F8030 requires only a +5V supply and is
available in 16-Lead SON, and SOL packages.
FEATURES
Ideal for:
- constant density recording applications
- magnetic tape recording
Programmable filter cutoff frequency
(c = 250 kHz to 2.5 MHz)
Programmable high frequency peaking
(0 to 9 dB boost at the filter cutoff frequency)
Matched normal and differentiated low-pass
outputs
Differential filter input and outputs
±
3.0% group delay variation from
0.2 c to 1.75 c, 0.25 MHz
c
2.5 MHz
Total harmonic distortion less than 1%
+5V only operation
16-Lead SON, and SOL packages
5 mW idle mode
A TDK Group Company
1
SSI 32F8030
Programmable
Electronic Filter
CAUTION: Use handling procedures necessary
for a static sensitive component.
BLOCK DIAGRAM
3
4
6
7
11
10
14
13
VO_NORM+
VCC1
VIN+
PWRON
VR
5
12
VCC2
IFP
VFP
8
9
FBST
GND2
VBP
VIN-
1
2
16
15
GND1
VO_NORM-
VO_DIFF+
VO_DIFF-
PIN DIAGRAM
Low Pass
Filter
Summer
VIN+
VIN-
High Pass
Filter
Low Pass
Filter
High Pass
Filter
Filter
Control
Variable
Atten.
VBP
VFP
FBST
VREF
BIAS
PWRON
VR
VO_NORM+
VO_NORM-
VO_DIFF+
VO_DIFF-
GND1
GND2
VCC2
IFP
VCC1
04/14/95 - rev.
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