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參數資料
| 型號： | SSTUA32866EC,557 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 鎖存器 |
| 英文描述： | 32866 SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PBGA96 |
| 封裝： | 13.50 X 5.50 MM, 1.05 MM HEIGHT, PLASTIC, SOT-536-1, LFBGA-96 |
| 文件頁數： | 1/28頁 |
| 文件大小： | 153K |
| 代理商： | SSTUA32866EC,557 |
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1.
General description
The SSTUA32866 is a 1.8 V congurable register specically designed for use on DDR2
memory modules requiring a parity checking function. It is dened in accordance with the
JEDEC standard for the SSTUA32866 registered buffer. The register is congurable
(using conguration pins C0 and C1) to two topologies: 25-bit 1 : 1 or 14-bit 1 : 2, and in
the latter conguration can be designated as Register A or Register B on the DIMM.
The SSTUA32866 accepts a parity bit from the memory controller on its parity bit
(PAR_IN) input, compares it with the data received on the DIMM-independent D-inputs
and indicates whether a parity error has occurred on its open-drain QERR pin
(active LOW). The convention is even parity, that is, valid parity is dened as an even
number of ones across the DIMM-independent data inputs combined with the parity input
bit.
The SSTUA32866 is packaged in a 96-ball, 6
× 16 grid, 0.8 mm ball pitch LFBGA package
(13.5 mm
× 5.5 mm).
2.
Features
I Congurable register supporting DDR2 up to 667 MT/s Registered DIMM applications
I Congurable to 25-bit 1 : 1 mode or 14-bit 1 : 2 mode
I Controlled output impedance drivers enable optimal signal integrity and speed
I Exceeds JESD82-7 speed performance (1.8 ns max. single-bit switching propagation
delay; 2.0 ns max. mass-switching)
I Supports up to 450 MHz clock frequency of operation
I Optimized pinout for high-density DDR2 module design
I Chip-selects minimize power consumption by gating data outputs from changing state
I Supports SSTL_18 data inputs
I Checks parity on the DIMM-independent data inputs
I Partial parity output and input allows cascading of two SSTUA32866s for correct parity
error processing
I Differential clock (CK and CK) inputs
I Supports LVCMOS switching levels on the control and RESET inputs
I Single 1.8 V supply operation (1.7 V to 2.0 V)
I Available in 96-ball, 13.5 mm × 5.5 mm, 0.8 mm ball pitch LFBGA package
3.
Applications
I 400 MT/s to 667 MT/s DDR2 registered DIMMs desiring parity checking functionality
SSTUA32866
1.8 V 25-bit 1 : 1 or 14-bit 1 : 2 congurable registered buffer
with parity for DDR2-667 RDIMM applications
Rev. 02 — 26 March 2007
Product data sheet
相關PDF資料 |
PDF描述 |
|---|---|
| SSTUA32866EC/G,551 | 32866 SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PBGA96 |
| SSTUA32866EC/G,557 | 32866 SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PBGA96 |
| SSTUAF32866BHLFT | 32866 SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PBGA96 |
| SSTUAF32869AHLFT | 32869 SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PBGA150 |
| SSTUB32864EC/G | 32864 SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PBGA96 |
相關代理商/技術參數 |
參數描述 |
|---|---|
| SSTUA32866EC-G | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:1.8 V 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer with parity for DDR2-667 RDIMM applications |
| SSTUA32S865 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:1.8 V 28-bit 1 : 2 registered buffer with parity for DDR2-667 RDIMM applications |
| SSTUA32S865BHLF | 功能描述:IC REGIST BUFF 25BIT DDR 160BGA RoHS:是 類別:集成電路 (IC) >> 邏輯 - 專用邏輯 系列:- 產品變化通告:Product Discontinuation 25/Apr/2012 標準包裝:1,500 系列:74SSTV 邏輯類型:DDR 的寄存緩沖器 電源電壓:2.3 V ~ 2.7 V 位數:14 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:48-TFSOP（0.240"，6.10mm 寬） 供應商設備封裝:48-TSSOP 包裝:帶卷 (TR) |
| SSTUA32S865BHLFT | 功能描述:IC REGIST BUFF 25BIT DDR 160BGA RoHS:是 類別:集成電路 (IC) >> 邏輯 - 專用邏輯 系列:- 產品變化通告:Product Discontinuation 25/Apr/2012 標準包裝:1,500 系列:74SSTV 邏輯類型:DDR 的寄存緩沖器 電源電壓:2.3 V ~ 2.7 V 位數:14 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:48-TFSOP（0.240"，6.10mm 寬） 供應商設備封裝:48-TSSOP 包裝:帶卷 (TR) |
| SSTUA32S865ET | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:1.8 V 28-bit 1 : 2 registered buffer with parity for DDR2-667 RDIMM applications |
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