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參數資料
| 型號： | SSTV16857DGV |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 通用總線功能 |
| 英文描述： | 14-bit SSTL_2 registered driver with differential clock inputs |
| 中文描述： | SSTV SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO48 |
| 封裝： | 4.40 MM, PLASTIC, SOT-480-1, TVSOP-48 |
| 文件頁數： | 1/7頁 |
| 文件大小： | 85K |
| 代理商： | SSTV16857DGV |
2005 Fairchild Semiconductor Corporation
DS500387
www.fairchildsemi.com
September 2000
Revised June 2005
S
SSTV16857
SSTVN16857
14-Bit Register with SSTL-2 Compatible I/O and Reset
General Description
The SSTV16857 is a 14-bit register designed for use with
184 and 232 pin PC1600, 2100, and 2700 DDR DIMM
applications. The SSTVN16857 is a 14-bit register
designed for use with 184 and 232 pin PC3200 DDR DIMM
applications. These devices have a differential input clock,
SSTL-2 compatible data inputs and a LVCMOS compatible
RESET input. These devices have been designed for com-
pliance with the JEDEC DDR module and register specifi-
cations.
The devices are fabricated on an advanced submicron
CMOS process and are designed to operate at power sup-
plies of less than 3.6V’s.
Features
I
Compliant with DDR-I registered module specifications
I
Operates at 2.5V
r
0.2V V
DD
I
SSTL-2 compatible input and output structure
I
Differential SSTL-2 compatible clock inputs
I
Low power mode when device is reset
I
Industry standard 48 pin TSSOP package
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter
“
X
”
to the ordering code.
Connection Diagram
Pin Descriptions
Truth Table
L
Logic LOW
H
Logic HIGH
X
Don
’
t Care, but not floating unless noted
n
LOW-to-HIGH Clock Transition
p
HIGH-to-LOW Clock Transition
Order Number
SSTV16857MTD
SSTVN16857MTD
(Preliminary)
Package Number
MTD48
MTD48
Package Description
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Pin Name
Q
1
-Q
14
D
1
-D
14
RESET
CK
Description
SSTL-2 Compatible Output
SSTL-2 Compatible Inputs
Asynchronous LVCMOS Reset Input
Positive Master Clock Input
CK
V
REF
V
DDQ
V
DD
Negative Master Clock Input
Voltage Reference Pin for SSTL Level Inputs
Power Supply Voltage for Output Signals
Power Supply Voltage for Inputs
RESET
L
D
n
X or
Floating
L
H
X
X
CK
X or
Floating
CK
X or
Floating
Q
n
L
H
H
H
H
n
p
L
H
Q
n
Q
n
n
p
L
H
H
L
相關PDF資料 |
PDF描述 |
|---|---|
| SSTV16857EV | 14-bit SSTL_2 registered driver with differential clock inputs |
| SSTV16857MTD | Voltage Regulator IC; Output Current:300mA; Output Voltage:5V; Package/Case:8-MSOP; Supply Voltage Max:6V; Current Rating:300mA; Leaded Process Compatible:No; Output Current Max:300mA; Output Voltage Max:5V |
| SSTVN16857 | 14-Bit Register with SSTL-2 Compatible I/O and Reset |
| SSTVN16857MTD | 14-Bit Register with SSTL-2 Compatible I/O and Reset |
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相關代理商/技術參數 |
參數描述 |
|---|---|
| SSTV16857DGV,112 | 功能描述:寄存器 14BT2.5VSSTL2 REG RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數量:1 最大時鐘頻率:36 MHz 傳播延遲時間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube |
| SSTV16857DGV,118 | 功能描述:寄存器 14BT2.5VSSTL2 REG RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數量:1 最大時鐘頻率:36 MHz 傳播延遲時間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube |
| SSTV16857DGV-T | 功能描述:寄存器 14BT2.5VSSTL2 REG DRIVR/DC INP RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數量:1 最大時鐘頻率:36 MHz 傳播延遲時間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube |
| SSTV16857EV | 功能描述:寄存器 14BIT 2.5V REG DRV W/DIFF RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數量:1 最大時鐘頻率:36 MHz 傳播延遲時間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube |
| SSTV16857EV,118 | 功能描述:寄存器 14BIT 2.5V REG DRIVER W/DIFF RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數量:1 最大時鐘頻率:36 MHz 傳播延遲時間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube |
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