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參數資料
| 型號： | SSTV16859G |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 通用總線功能 |
| 英文描述： | Voltage Regulator IC; Output Current:300mA; Package/Case:8-MSOP; Supply Voltage Max:6V; Current Rating:300mA; Leaded Process Compatible:No; Output Current Max:300mA; Output Voltage Max:5V; Output Voltage Min:1.215V |
| 中文描述： | SSTV SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PBGA96 |
| 封裝： | 5.50 MM, PLASTIC, FBGA-96 |
| 文件頁數： | 1/8頁 |
| 文件大小： | 168K |
| 代理商： | SSTV16859G |
2002 Fairchild Semiconductor Corporation
DS500414
www.fairchildsemi.com
March 2001
Revised July 2002
S
SSTV16859
Dual Output 13-Bit Register with
SSTL-2 Compatible I/O and Reset
General Description
The SSTV16859 is a dual output 13-bit register designed
for use with 184 and 232 pin DDR-1 memory modules. The
device has a differential input clock, SSTL-2 compatible
data inputs and a LVCMOS compatible RESET input. The
device has been designed to meet the JEDEC DDR mod-
ule register specifications.
The device has been fabricated on an advanced sub-
micron CMOS process and is designed to operate at power
supplies of less than 3.6V’s.
Features
I
Compliant with DDR-I registered module specifications
I
Operates at 2.5V
±
0.2V V
DD
I
SSTL-2 compatible input structure
I
SSTL-2 compliant output structure
I
Differential SSTL-2 compatible clock inputs
I
Low power mode when device is reset
I
Industry standard 64 pin TSSOP package
I
Also packaged in plastic Fine-Pitch Ball Grid Array
(FBGA)
Ordering Code:
Note 1:
Ordering code
“
G
”
indicates Trays.
Note 2:
Devices also available in Tape and Reel. Specify by appending the suffix letter
“
X
”
to the ordering code.
Order Number
SSTV16859G
(Note 1)(Note 2)
SSTV16859MTD
(Note 2)
Package Number
BGA96A
Package Description
96-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
MTD64
64-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
相關PDF資料 |
PDF描述 |
|---|---|
| SSTV16859MTD | Dual Output 13-Bit Register with SSTL-2 Compatible I/O and Reset |
| SSTVF16857 | DDR PC1600-PC3200 14-bit SSTL_2 registered driver with differential clock inputs |
| SSTVF16857DGG | DDR PC1600-PC3200 14-bit SSTL_2 registered driver with differential clock inputs |
| SSTVF16857DGV | DDR PC1600-PC3200 14-bit SSTL_2 registered driver with differential clock inputs |
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相關代理商/技術參數 |
參數描述 |
|---|---|
| SSTV16859GX | 功能描述:寄存器 13-Bit Register DO SSTL-2 Comp RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數量:1 最大時鐘頻率:36 MHz 傳播延遲時間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube |
| SSTV16859MTD | 功能描述:寄存器 13-Bit Register DO SSTL-2 Comp RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數量:1 最大時鐘頻率:36 MHz 傳播延遲時間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube |
| SSTV16859MTDX | 功能描述:寄存器 13-Bit Register DO SSTL-2 Comp RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數量:1 最大時鐘頻率:36 MHz 傳播延遲時間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube |
| SSTVA16857AG | 功能描述:IC REGIST BUFF 14BIT DDR 48TSSOP RoHS:否 類別:集成電路 (IC) >> 邏輯 - 專用邏輯 系列:- 產品變化通告:Product Discontinuation 25/Apr/2012 標準包裝:1,500 系列:74SSTV 邏輯類型:DDR 的寄存緩沖器 電源電壓:2.3 V ~ 2.7 V 位數:14 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:48-TFSOP（0.240"，6.10mm 寬） 供應商設備封裝:48-TSSOP 包裝:帶卷 (TR) |
| SSTVA16857AGLF | 功能描述:寄存器 RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數量:1 最大時鐘頻率:36 MHz 傳播延遲時間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube |
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