
IMPROVED 486DX/DX2 PERFORMANCE
- Clock doubled core speeds up to 80 MHz
- Integrated FPU 10% faster than 80486DX
- Up to 50 MHz bus speeds for fast local bus systems
INDUSTRY STANDARD 486 COMPATIBILITY
- 486DX socket and instruction set compatible
- Runs DOS, Windows, OS/2, UNIX
- Standard 168-pin PGA
ON-CHIP 8-KBYTE WRITE-BACK CACHE
- Up to 15% higher performance than write-through
(PC Bench 8.0, 80MHZ)
- Industry-wide write-back chipset suppor
- Burst-mode write capability
- Configurable as write-back or write-through
ADVANCED POWER MANAGEMENT
- Fast SMI interrupt with separate memory space
- Fully static design permits dynamic clock control
- Software or hardware initiated low power suspend
- Automatic FPU power-down mode
The SGS-THOMSON ST486DX/DX2 5 volt CPUs are advanced
486DX/DX2 compatible processors. These CPUs incorporate an
on-chip 8KByte write-back cache and an integrated math coproc-
essor.
The on-chip write-back cache allowsup to 15% higher performance
by eliminating unnecessary external write cycles. On traditional
write-through CPUs, these external write cycles can create bus
bottlenecks affecting system wide performance.
The integrated floating point unit, improves performance up to 10%
over the 80486DX as measured using Power Meter Whetstone test.
These processors are designed to meet the power management
requirements in the newest generation of low-power desktops and
notebooks. Power is saved by taking advantage of advanced power
management features such as static circuitry, SMM, and automatic
FPU power-down. Fast entry and exit of SMM allows frequent use of
the SMM feature without noticeable performance degradation.
This CPU family maintains compatibility with the installed base of
x86 software and provides essential socket compatibility with the
486DX/DX2
Decoder
Microcode ROM
Address
Sequencer
16-byte
Execution Unit
Limit
Unit
Multiplier
Unit
3-Input
Adder
Shift
Unit
Register
File
Data
Bus
Byte
& I/O
Regs
Muxes
Memory
Management
Unit
Prefetch
Unit
8 KByte
Instr/Data
Cache
Linear Address Bus
Memory
Instruction Address Bus
Data AddressBus
Address
Bus
Control
Buffers
Data
Control
Branch Control
Control
Immediate
Control
Immediate
D31-D0
A31-A2
ROM
Queue
Buffers
Instruction
32
Execution Pipeline
8 Write
32
Prefetch
1738600
Data Bus
Buffers
BE3#-BE0#
SUSP#
SUSPA#
CLK
SMI#
SMADS#
FPU
Cache and Memory
Management
486DX Compatible
Bus Interface
SMM,
Suspend
Mode
and
Clock
Control
Core
Clock
Bus
Clock
Control
ST486DX/DX2
5 Volt CPUs
PRELIMINARY DATA
1