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參數(shù)資料
| 型號： | ST75C185CTR |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | LOW POWER MULTIPLE RS-232 DRIVERS AND RECEIVERS |
| 中文描述： | 多重低功耗的RS - 232驅(qū)動器和接收 |
| 文件頁數(shù)： | 1/13頁 |
| 文件大小： | 111K |
| 代理商： | ST75C185CTR |
ST75C185
LOW POWER
MULTIPLE RS-232 DRIVERS AND RECEIVERS
TARGET DATA
June 2000
I
MEETS STANDARDEIA-232-E
I
SINGLECHIPWITHINTERFACEBETWEEN
UARTAND SERIALPORT CONNECTOR
I
LESSTHAN 20mWQUIESCENTPOWER
CONSUMPTION
I
WIDEDRIVERSUPPLYVOLTAGE:7 TO13.2V
I
DRIVEROUTPUTSLEWRATE LIMITEDTO
30V/
μ
sMAX
I
RECEIVERINPUT HYSTERESIS:1.1TYP
I
PUSH-PULLRECEIVEROUTPUTS
I
ONCHIPRECEIVER1
μ
s NOISEFILTER
I
FUNCTIONALLYINTERCHANGEABLEWITH
STMST75185
I
ESDPROTECTION:
±
10KVHUMAN BODY
MODEL
DESCRIPTION
The ST75C185 is low power BICMOS device
containing three independent drivers and five
receivers that is used to interface data terminal
equipment (DTE) with data circuit-terminating
equipment
(DCE).
This
designed
to
conform
ANSI/EIA-232-E. The drivers have a controlled
output slew rate that is limited to a maximum of
30V/
μ
s and the receivers have filters that reject
input noise pulses that are shorter than 1
μ
s. Both
device
has
Standards
been
to
these features eliminate the need of external
components.
The ST75C185 hasn’t a power sequence fault
condition. It has been designed using low-power
techniquesin a BICMOStecnology.
In most application the receivers contained in this
device will interface to single inputs peripheral
devices
such
as
microprocessors.
By
using
peripheral devices are usuallly insensitive to the
transition times of the input signals. If this is not
the case, or for other uses, it is recommended
that the ST75C185 receiver outputs be buffered
by single gates of the HCMOS, ALS or 74F logic
families.
ACEs,
UARTs
or
sampling,
such
PIN CONNECTION IEC LOGICSYMBOL AND LOGIC DIAGRAM
(Micro Package)
(Plastic Package)
(TSSOPPackage)
1/13
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