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參數資料
型號: STE10/100E
廠商: STMICROELECTRONICS
元件分類: 微控制器/微處理器
英文描述: 1 CHANNEL(S), 100M bps, LOCAL AREA NETWORK CONTROLLER, PQFP128
封裝: 14 X 20 MM, 2.70 MM HEIGHT, PLASTIC, QFP-128
文件頁數: 1/66頁
文件大小: 396K
代理商: STE10/100E
1/66
STE10/100A
November 2002
REVISION: A07
Details are subject to change without notice.
1.0 DESCRIPTION
The STE10/100A is a high performance PCI Fast
Ethernet controller with integrated physical layer in-
terface for 10BASE-T and 100BASE-TX application.
It was designed with advanced CMOS technology to
provide glueless 32-bit bus master interface for PCI
bus, boot ROM interface, CSMA/CD protocol for Fast
Ethernet, as well as the physical media interface for
100BASE-TX of IEEE802.3u and 10BASE-T of
IEEE802.3. The auto-negotiation function is also
supported for speed and duplex detection.
The STE10/100A provides both half-duplex and full-
duplex operation, as well as support for full-duplex
flow control. It provides long FIFO buffers for trans-
mission and receiving, and early interrupt mecha-
nism to enhance performance. The STE10/100A also
supports ACPI and PCI compliant power manage-
ment function.
2.0 FEATURES
2.1 Industry standard
s
IEEE802.3u 100BASE-TX and IEEE802.3
10BASE-T compliant
s
Support for IEEE802.3x flow control
s
IEEE802.3u Auto-Negotiation support for
10BASE-T and 100BASE-TX
s
PCI bus interface Rev. 2.2 compliant
s
ACPI and PCI power management standard
compliant
s
Support for PC99 wake on LAN
s
Provides 32-bit PCI bus master data transfer at
PCI clocks of 20-33 MHz
s
Provides writeable EEPROM/ Boot Rom
Interface
s
Provides independent transmission and
receiving FIFOs, each 2k bytes long
s
Supports big endian or little endian byte
ordering
ORDERING INFO:
STE10/100A - Commercial Temp version
STE10/100E - Industrial Temp version
PQFP128 (14x20x2.7mm)
PCI 10/100 ETHERNET CONTROLLER
WITH INTEGRATED PHY (3.3V)
Figure 1. STE10/100A Block Diagram
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