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參數(shù)資料
| 型號： | STK3NA50 |
| 廠商： | 意法半導體 |
| 英文描述： | N - CHANNEL ENHANCEMENT MODE FAST POWER MOS TRANSISTOR |
| 中文描述： | ? -快速通道增強型功率MOS器件 |
| 文件頁數(shù)： | 1/10頁 |
| 文件大小： | 180K |
| 代理商： | STK3NA50 |
STK3NA50
N - CHANNEL ENHANCEMENT MODE
FAST POWER MOS TRANSISTOR
I
TYPICAL R
DS(on)
= 2.4
I
±
30V GATE TO SOURCE VOLTAGE RATING
I
100% AVALANCHE TESTED
I
REPETITIVE AVALANCHE DATA AT 100
o
C
I
LOW INTRINSIC CAPACITANCES
I
GATE GHARGE MINIMIZED
I
REDUCED THRESHOLD VOLTAGE SPREAD
DESCRIPTION
This series of POWER MOSFETS represents the
most advanced high voltage technology. The op-
timized cell layout coupled with a new proprietary
edge termination concur to give the device low
R
DS(on)
and gate charge, unequalled ruggedness
and superior switching performance.
APPLICATIONS
I
HIGH CURRENT, HIGH SPEED SWITCHING
I
SWITCH MODE POWERSUPPLIES (SMPS)
I
DC-AC CONVERTERS FOR WELDING
EQUIPMENT AND UNINTERRUPTIBLE
POWER SUPPLIES AND MOTOR DRIVE
INTERNAL SCHEMATIC DIAGRAM
TYPE
V
DSS
R
DS(on)
< 3
I
D
STK3NA50
500 V
2.7 A
12
3
SOT-82
SOT-194
(option)
November 1996
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
V
DS
Drain-source Voltage (V
GS
= 0)
Drain- gate Voltage (R
GS
= 20 k
)
Gate-source Voltage
Drain Current (continuous) at T
c
= 25
o
C
Drain Current (continuous) at T
c
= 100
o
C
500
V
V
DGR
500
±
30
2.7
V
V
GS
V
I
D
A
I
D
1.7
A
I
DM
(
)
P
tot
Drain Current (pulsed)
Total Dissipation at T
c
= 25
o
C
10.8
A
50
W
Derating Factor
0.4
W/
o
C
o
C
o
C
T
stg
Storage Temperature
-65 to 150
T
j
Max. Operating Junction Temperature
(
) Pulsewidth limited by safe operating area
150
1
2
3
1/10
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