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參數資料
型號: STP2200ABGA-100
元件分類: 存儲控制器/管理單元
英文描述: 256M X 8, DRAM CONTROLLER, PBGA225
封裝: PLASTIC, BGA-225
文件頁數: 1/36頁
文件大小: 433K
代理商: STP2200ABGA-100
DATA SHEET
1
STP2200ABGA
USC
Uniprocessor System Controller
DESCRIPTION
The Uniprocessor System Controller (USC) has a DRAM memory controller and functions to regulate the
ow of requests and data on the UPA bus. It also controls the resets going to all UPA clients.
The USC is used as the system controller of a complete Uniprocessor UltraSPARC system.
Note:
Instead of using the U2S, the USC can also be used with the UPA to PCI-bus; I/O interface
controller (U2P)
Note:
This data sheet refers to the UPA to System I/O interface. The UPA to PCI bus Interface controller
(U2P) can be substituted where U2S appears.
Features
Benets
Controls up to eight standard SS-10/SS-20-type DRAM
SIMMs
Standard workstation memory
Supports various memory SIMM organizations: 16 MB, 64
MB, and 256 MB as well as dual-stacked 128-MB SIMMs
Flexibility
Controls and generates a number of resets for the system
High integration
Programmed via a standard 8-bit asynchronous interface
(EBus)
Allows design of low-cost, low-chip-count embedded
systems
JTAG interface allows full chip scan
Ease of design and testability
225-pin ABGA package
Low cost
UPA Devices
Abbreviations
Part Number
Description
USC
SC_UP
STP 2200ABGA
Uniprocessor System Controller
RIC
RISC
STP2210QFP
Reset/Interrupt/Clock Controller
U2S
SYSIO
STP2220ABGA
UPA to SBus I/O interface controller
U2P
Psycho
STP2222ABGA
UPA to PCI bus I/O Interface controller
XBI
BMX
STP2230SOP
Crossbar Data Path
July 1997
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相關代理商/技術參數
參數描述
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