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參數(shù)資料
| 型號(hào)： | STPC0380BTI3 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | PC Compatible Embeded Microprocessor |
| 中文描述： | PC兼容嵌入式微處理器 |
| 文件頁(yè)數(shù)： | 1/51頁(yè) |
| 文件大小： | 726K |
| 代理商： | STPC0380BTI3 |
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STPC CONSUMER
PC Compatible Embeded Microprocessor
1/51
8/2/00
Issue 1.2
Figure 1. Logic Diagram
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POWERFUL X86 PROCESSOR
64-BIT BUS ARCHITECTURE
64-BIT DRAM CONTROLLER
SVGA GRAPHICS CONTROLLER
UMA ARCHITECTURE
VIDEO SCALER
DIGITAL PAL/NTSC ENCODER
VIDEO INPUT PORT
CRT CONTROLLER
135MHz RAMDAC
3 LINE FLICKER FILTER
SCAN CONVERTER
PCI MASTER / SLAVE / ARBITER CTRL
ISA MASTER/SLAVE INTERFACE
IDE CONTROLLER
DMA CONTROLLER
INTERRUPT CONTROLLER
TIMER / COUNTERS
POWER MANAGEMENT
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STPC CONSUMER OVERVIEW
The STPC Consumer integrates a standard 5th
generation x86 core, a DRAM controller, a graph-
ics subsystem, a video pipeline and support logic
including PCI,ISA and IDE controllers to provide a
single Consumer orientated PC compatible sub-
system on a single device.
The device is based on a tightly coupled Unified
Memory Architecture (UMA), sharing the same
memory array between the CPU main memory
and the graphics and video frame buffers.
Extra facilities are implemented to handle video
streams. Features include smooth scaling and
color space conversion of the video input stream
and mixing with graphics data. The chip also in-
cludes a built-in digital TV encoder and anti-flicker
filters that allow stable, high-quality display on
standard PAL or NTSC television sets without ad-
ditional components.
The STPC Consumer is packaged in a 388 Plastic
Ball Grid Array (PBGA).
PBGA388
x86
Core
Host I/F
DRAM
CTRL
VIP
PCI
m/s
PCIBUS
ISA
m/s
EIDE
PCI
m/s
ISABUS
CRTC
HW Cursor
Monitor
TVOutput
SYNCOutput
Color Space
Converter
Color
Key
Chroma
Key
Video
pipeline
2D
SVGA
CCIRInput
EIDE
AntiFlicker
IPC
Digital
PAL/
NTSC
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