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參數資料
| 型號： | STTA1JB-FREQ |
| 元件分類： | XO, clock |
| 英文描述： | CRYSTAL OSCILLATOR, CLOCK, 0.25 MHz - 35 MHz, TTL OUTPUT |
| 文件頁數： | 2/2頁 |
| 文件大小： | 126K |
| 代理商： | STTA1JB-FREQ |
All specifications are subject to change without notice.
Crystal Clock Oscillator
Technical Data
DS-108
REV K
SaRonix
3.3 & 5V, HCMOS, ACMOS, TTL
STA / STT Series
Package Details
21.0
.825
max
5.08
.200
.46±.08
.018±.003
15.24±.13
.600±.005
7.75
.305
(4) Glass
Insulators
Pin 1
Tri-State
Control
Pin 7
GND
Pin 14
+5 or +3.3 VDC
Pin 8 Output
FULL SIZE PACKAGE
0.9
.036
max
13.0
.510
max
Denotes Pin 1
SARONIX
XTAL OSC
max
Marking Format **
Includes Date Code, Frequency & Part Number
HALF SIZE PACKAGE
5.08
.200
max
13.0
.510
max
0.9
.036
max
.46±.08
.018±.003
7.62±.20
.300±.008
Glass Insulators
Pin 5
Output
Pin 1
Tri-State
Pin 4
GND
120°
13.0
.510
max
7.62±.20
.300±.008
1.5
.059
Denotes Pin 1
SARONIX
Marking Format **
Includes Date Code, Frequency & Part Number
Scale: None (Dimensions in
)
mm
inches
** Exact location of items may vary
Output Waveform
Tri-State Logic Table
Pin 1 Input
Logic 1 or NC
Logic 0 or GND
Output
Standard Logic
Oscillation
High Impedance
Required Input Levels on Pin 1:
Logic 1 = 2.2V min
Logic 0 = 0.8V max
6.35±.51
.250±.020
6.35±.51
.250±.020
Tr
Tf
Tr
Tf
TTL
VDD
GND
SYMMETRY
LOGIC 0
LOGIC 1
80% VDD
50% VDD
20% VDD
ACMOS
1.5 VDC
2.5 VDC
0.5 VDC
Test Circuit
POWER
SUPPLY
Pin 7 (4)
POWER
SUPPLY
ACMOS
95
Load
0.01 F
95
TEST
POINT
VCC
OSCILLATOR
Pin 8 (5)
Pin 7 (4)
Pin 14 (8)
OUT
GND
Pin 1 ( 1 )*
.01 F
TRI-STATE INPUT
(current limited on fixture)
*( ) Indicates pin numbers for half-size package
95
ACMOS TEST CIRCUIT (3.3V operation)
mA
M
V M
VCC
OSCILLATOR
Pin 8 (5)
Pin 14 (8)
.01 F
OUT
GND
Pin 1 ( 1 )*
ACMOS
50
Load
0.01 F
56
TEST
POINT
TRI-STATE INPUT
(current limited on fixture)
*( ) Indicates pin numbers for half-size package
50
ACMOS TEST CIRCUIT (5V operation)
mA
M
V M
max
SaRonix
141 Jefferson Drive Menlo Park, CA 94025 USA 650-470-7700 800-227-8974 Fax 650-462-9894
Pin 14
+5 or +3.3 VDC
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