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參數(shù)資料
| 型號(hào)： | STVA16857AGLF |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類(lèi)： | 鎖存器 |
| 英文描述： | SSTV SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO48 |
| 封裝： | 6.10 MM WIDTH, 0.50 MM PITCH, MO-153, LEAD FREE, TSSOP-48 |
| 文件頁(yè)數(shù)： | 1/13頁(yè) |
| 文件大小： | 126K |
| 代理商： | STVA16857AGLF |
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Integrated
Circuit
Systems, Inc.
ICSSSTVA16857
0932A—05/12/04
Pin Configuration
DDR 14-Bit Registered Buffer
Truth Table
1
Block Diagram
Notes:
1.
H = High Signal Level
L = Low Signal Level
↑ = Transition LOW-to-HIGH
↓ = Transition HIGH -to LOW
X = Irrelevant
2.
Output level before the indicated
steady state input conditions were
established.
s
t
u
p
n
Is
t
u
p
t
u
O
Q
#
T
E
S
E
RK
L
C#
K
L
CD
Q
L
r
o
X
g
n
i
t
a
o
l
F
r
o
X
g
n
i
t
a
o
l
F
r
o
X
g
n
i
t
a
o
l
F
L
H
↑↓
HH
H
↑↓
LL
HH
r
o
LH
r
o
LX
Q0 )
2
(
48-Pin TSSOP
6.10 mm. Body, 0.50 mm. pitch = TSSOP
Recommended Applications:
DDR Memory Modules
Provides complete DDR DIMM logic solution with
ICS93V857 or ICS95V857
SSTL_2 compatible data registers
DDR400 recommended (backward compatible to
DDR200/266/333)
Product Features:
Exceeds "SSTVN16857" performance
Differential clock signal
Meets SSTL_2 signal data
Supports SSTL_2 class I & II specifications
Low-voltage operation
- VDD = 2.3V to 2.7V
48 pin TSSOP package
CLK
CLK#
38
39
48
35
34
D1
VREF
RESET#
To 13 Other Channels
Q1
1
CLK
R
D1
Q1
Q2
GND
VDDQ
Q3
Q4
Q5
GND
VDDQ
Q6
Q7
VDDQ
GND
Q8
Q9
VDDQ
GND
Q10
Q11
Q12
VDDQ
GND
Q13
Q14
D1
D2
GND
VDD
D3
D4
D5
D6
D7
CLK#
CLK
VDD
GND
VREF
RESET#
D8
D9
D10
D11
D12
VDD
GND
D13
D14
ICSSSTVA16857
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
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