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參數資料
| 型號： | SY100E143JZ |
| 廠商： | MICREL INC |
| 元件分類： | 通用總線功能 |
| 英文描述： | 9-BIT HOLD REGISTER |
| 中文描述： | 100E SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PQCC28 |
| 封裝： | LEAD FREE, PLASTIC, LCC-28 |
| 文件頁數： | 1/4頁 |
| 文件大?。?/td> | 71K |
| 代理商： | SY100E143JZ |
1
SY10E143
SY10E143
SY100E143
Micrel, Inc.
M9999-032006
hbwhelp@micrel.com or (408) 955-1690
I
700MHz min. operating frequency
I
Extended 100E V
EE
range of –4.2V to –5.5V
I
9 bits wide for byte-parity applications
I
Asynchronous Master Reset
I
Dual clocks
I
Fully compatible with industry standard 10KH,
100K ECL levels
I
Internal 75k
input pulldown resistors
I
Fully compatible with Motorola MC10E/100E143
I
Available in 28-pin PLCC package
FEATURES
9-BIT HOLD
REGISTER
The SY10/100E143 are high-speed 9-bit hold registers
designed for use in new, high-performance ECL systems.
The E143 can hold current data or load new data. The nine
inputs, D
0
-D
8
, accept parallel input data.
The SEL (Select) control pin serves to determine the
mode of operation; either HOLD or LOAD. The input data
has to meet the set-up time before being clocked into the
nine input registers on the rising edge of CLK
1
or CLK
2
.
The MR (Master Reset) control signal asynchronously
resets all nine registers to a logic LOW when a logic HIGH
is applied to MR.
The E143 is designed for applications requiring high-
speed registers, pipeline registers, synchronous operation,
and is also suitable for byte-wide parity.
DESCRIPTION
PIN NAMES
Pin
Function
D
0
-D
8
Parallel Data Inputs
SEL
Mode Select Input
CLK
1
, CLK
2
Clock Inputs
MR
Master Reset
Q
0
-Q
8
Data Outputs
NC
No Connection
V
CCO
V
CC
to Output
BLOCK DIAGRAM
D
Q
0
Q
1
Q
2
Q
3
Q
4
Q
5
Q
6
Q
7
Q
8
SEL
MR
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
8
CLK1
CLK2
D
D
R
D
R
D
R
D
R
D
R
D
R
D
R
R
R
MUX
MUX
MUX
MUX
MUX
MUX
MUX
MUX
MUX
Rev.: F
Issue Date:
Amendment: /0
March 2006
相關PDF資料 |
PDF描述 |
|---|---|
| SY100E143JZTR | 9-BIT HOLD REGISTER |
| SY100E150JZ | 6-BIT D LATCH |
| SY100E150JZTR | 6-BIT D LATCH |
| SY100E151 | 6-BIT D REGISTER |
| SY100E151JZ | 6-BIT D REGISTER |
相關代理商/技術參數 |
參數描述 |
|---|---|
| SY100E143JZ TR | 功能描述:寄存器 9-bit Hold Register (Lead Free) RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數量:1 最大時鐘頻率:36 MHz 傳播延遲時間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube |
| SY100E143JZTR | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:9-BIT HOLD REGISTER |
| SY100E150 | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:6-BIT D LATCH |
| SY100E150JC | 功能描述:IC LATCH D 6-BIT 28-PLCC RoHS:否 類別:集成電路 (IC) >> 邏輯 - 鎖銷 系列:100E 產品變化通告:Product Discontinuation 09/Dec/2010 標準包裝:1,500 系列:74VCX 邏輯類型:D 型透明鎖存器 電路:8:8 輸出類型:三態 電源電壓:1.8 V ~ 3.6 V 獨立電路:2 延遲時間 - 傳輸:1.5ns 輸出電流高，低:6mA，6mA 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-TFSOP（0.240"，6.10mm 寬） 供應商設備封裝:48-TSSOP 包裝:帶卷 (TR) |
| SY100E150JCTR | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:6-BIT D LATCH |
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