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參數(shù)資料
| 型號： | SY100E151JCTR |
| 廠商： | MICREL INC |
| 元件分類： | 通用總線功能 |
| 英文描述： | 6-BIT D REGISTER |
| 中文描述： | 100E SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PQCC28 |
| 封裝： | PLASTIC, LCC-28 |
| 文件頁數(shù)： | 1/4頁 |
| 文件大小： | 61K |
| 代理商： | SY100E151JCTR |
I
1100MHz toggle frequency
I
Extended 100E V
EE
range of –4.2V to –5.46V
I
Differential outputs
I
Asynchronous Master Reset
I
Dual clocks
I
Fully compatible with industry standard 10KH,
100K ECL levels
I
Internal 75K
input pulldown resistors
I
Fully compatible with Motorola MC10E/100E151
I
Available in 28-pin PLCC package
FEATURES
6-BIT D
REGISTER
The SY10/100E151 offer 6 edge-triggered, high-speed,
master-slave D-type flip-flops with differential outputs,
designed for use in new, high-performance ECL systems.
The two external clock signals (CLK
1
, CLK
2
) are gated
through a logical OR operation before use as clocking
control for the flip-flops. Data is clocked into the flip-flops
on the rising edge of either CLK
1
or CLK
2
(or both). When
both CLK
1
and CLK
2
are at a logic LOW, data enters the
master and is transferred to the slave when either CLK
1
or
CLK
2
(or both) go HIGH.
The MR (Master Reset) signal operates asynchronously
to make all Q outputs go to a logic LOW.
DESCRIPTION
SY10E151
SY100E151
Rev.: D
Issue Date: November, 1998
Amendment: /0
BLOCK DIAGRAM
Pin
Function
D
0
–D
5
Data Inputs
CLK
1
, CLK
2
Clock Inputs
MR
Master Reset
Q
0
–Q
5
True Outputs
Q
0
–Q
5
Inverting Outputs
V
CCO
V
CC
to Output
PIN NAMES
PIN CONFIGURATION
D
R
D
R
D
R
D
R
D
R
D
R
M
R
D
0
CLK
1
CLK
2
D
1
D
2
D
3
D
4
D
5
Q
0
Q
0
Q
1
Q
1
Q
2
Q
2
Q
3
Q
3
Q
4
Q
4
Q
5
Q
5
V
EE
D
2
D
5
D
4
D
3
D
1
D
0
Q
5
26
27
28
1
2
3
4
18
17
16
15
14
13
12
25 24 23 22 21 20 19
5
6
7
8
9
10 11
V
C
Q
1
Q
4
Q
4
V
CC
Q
3
Q
3
Q
2
Q
2
V
C
PLCC
TOP VIEW
J28-1
M
N
C
1
Q
1
Q
0
Q
0
V
C
N
C
2
Q
5
1
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SY10E151 | 6-BIT D REGISTER |
| SY10E155JC | 6-BIT 2:1 MUX-LATCH |
| SY10E155 | 6-BIT 2:1 MUX-LATCH |
| SY10E155JCTR | 6-BIT 2:1 MUX-LATCH |
| SY10E156 | 3-BIT 4:1 MUX-LATCH |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SY100E151JI | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:6-BIT D REGISTER |
| SY100E151JITR | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:6-BIT D REGISTER |
| SY100E151JZ | 功能描述:寄存器 6-bit D Register (Lead Free) RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數(shù)量:1 最大時鐘頻率:36 MHz 傳播延遲時間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube |
| SY100E151JZ TR | 功能描述:寄存器 6-bit D Register (Lead Free) RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數(shù)量:1 最大時鐘頻率:36 MHz 傳播延遲時間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube |
| SY100E151JZTR | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:6-BIT D REGISTER |
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