參數資料
| 型號： | SY100E160JC |
| 廠商： | Micrel Inc |
| 文件頁數： | 1/5頁 |
| 文件大小： | 0K |
| 描述： | IC PARITY GEN/CHKER 12BIT 28PLCC |
| 標準包裝： | 38 |
| 系列： | 100E |
| 邏輯類型： | 奇偶校驗發生器/校驗器 |
| 電路數： | 12 位 |
| 電源電壓： | 4.2 V ~ 5.5 V |
| 工作溫度： | 0°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-LCC（J 形引線） |
| 供應商設備封裝： | 28-PLCC |
1
SY10E160
SY100E160
Micrel, Inc.
M9999-032006
hbwhelp@micrel.com or (408) 955-1690
s Provides odd-HIGH parity of 12 inputs
s Extended 100E VEE range of –4.2V to –5.5V
s Output register with Shift/Hold capability
s 900ps max. D to Q, /Q output
s Enable control
s Asynchronous Register Reset
s Differential outputs
s Fully compatible with industry standard 10KH,
100K ECL levels
s Internal 75K
input pulldown resistors
s Fully compatible with Motorola MC10E/100E160
s Available in 28-pin PLCC package
FEATURES
12-BIT PARITY
GENERATOR/CHECKER
The SY10/100E160 are high-speed, 12-bit parity
generator/checkers with differential outputs, for use in
new, high-performance ECL systems. The output Q takes
on a logic HIGH value only when an odd number of inputs
are at a logic HIGH. A logic HIGH on the enable input (EN)
forces the output Q to a logic LOW.
An additional feature of the E160 is the output register.
Two multiplexers and their associated signals control the
register input by providing the option of holding present
data, loading the new parity data or shifting external data
in. To hold the present data, the Hold signal (HOLD) must
be at a logic LOW level. If the HOLD signal is at a logic
HIGH, the data present at the Q output is passed through
the first multiplexer. Taking the Shift signal (SHIFT) to a
logic HIGH will shift the data at the S-IN pin into the output
register. If the SHIFT signal is at a logic LOW, the output
of the first multiplexer is then passed through to the register.
The register itself is clocked on the rising edge of CLK1
or CLK2 (or both). The presence of a logic HIGH on the
reset pin (R) forces the register output Y to a logic LOW.
DESCRIPTION
SY10E160
SY100E160
Rev.: F
Amendment: /0
Issue Date:
March 2006
BLOCK DIAGRAM
Q
MUX
SEL
Y
0
1
MUX
SEL
0
1
R
D
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
CLK1
CLK2
S-IN
SHIFT
R
EN
HOLD
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相關代理商/技術參數 |
參數描述 |
|---|---|
| SY100E160JCTR | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:12-BIT PARITY GENERATOR/CHECKER |
| SY100E160JZ | 功能描述:IC PARITY GEN/CHKER 12BIT 28PLCC RoHS:是 類別:集成電路 (IC) >> 邏輯 - 奇偶校驗發生器和校驗器 系列:100E 產品變化通告:Product Obsolescence 30/Sept/2009 標準包裝:25 系列:10H 邏輯類型:奇偶校驗發生器/校驗器 電路數:12 位 輸出電流高，低:- 電源電壓:4.94 V ~ 5.46 V 工作溫度:0°C ~ 75°C 安裝類型:通孔 封裝/外殼:16-DIP（0.300"，7.62mm） 供應商設備封裝:16-DIP |
| SY100E160JZ TR | 功能描述:IC PARITY GEN/CHKER 12BIT 28PLCC RoHS:是 類別:集成電路 (IC) >> 邏輯 - 奇偶校驗發生器和校驗器 系列:100E 產品變化通告:Product Obsolescence 30/Sept/2009 標準包裝:25 系列:10H 邏輯類型:奇偶校驗發生器/校驗器 電路數:12 位 輸出電流高，低:- 電源電壓:4.94 V ~ 5.46 V 工作溫度:0°C ~ 75°C 安裝類型:通孔 封裝/外殼:16-DIP（0.300"，7.62mm） 供應商設備封裝:16-DIP |
| SY100E160JZTR | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:12-BIT PARITY GENERATOR/CHECKER |
| SY100E163 | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:2-BIT 8:1 MULTIPLEXER |
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