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參數資料
| 型號： | SY100E336JZTR |
| 廠商： | MICREL INC |
| 元件分類： | 通用總線功能 |
| 英文描述： | 3-BIT REGISTERED BUS TRANSCEIVER |
| 中文描述： | 100E SERIES, 3-BIT REGISTERED TRANSCEIVER, INVERTED OUTPUT, PQCC28 |
| 封裝： | LEAD FREE, PLASTIC, LCC-28 |
| 文件頁數： | 1/4頁 |
| 文件大小： | 73K |
| 代理商： | SY100E336JZTR |
1
SY10E336
SY10E336
SY100E336
Micrel, Inc.
M9999-032206
hbwhelp@micrel.com or (408) 955-1690
FEATURES
I
25
cutoff bus output
I
Extended 100E V
EE
range of –4.2V to –5.5V
I
50
receiver output
I
Transmit and receive registers
I
1500ps max. clock to bus
I
1000ps max. clock to Q
I
Internal edge slow-down capacitors on bus outputs
I
Additional package ground pins
I
Fully compatible with industry standard 10KH,
100K ECL levels
I
Internal 75K
input pulldown resistors
I
Fully compatible with Motorola MC10E/100E336
I
Available in 28-pin PLCC package
DESCRIPTION
The SY10/100E336 offer three bus transceivers with
both transmit and receive registers and are designed for
use in new, high-performance ECL systems. The bus
outputs (BUS
0
- BUS
2
) are designed to drive a 25
bus.
The receive outputs (Q
0
– Q
2
) are specified for 50
. The
bus outputs feature a normal logic HIGH level (V
OH
) and a
cutoff LOW level when at a logic LOW. At cutoff, the outputs
go to –2.0V and the output emitter-follower is “off”,
presenting a high impedance to the bus. The bus outputs
have edge slow-down capacitors.
The Transmit Enable pins (TEN) determine whether
current data is held in the transmit register or new data is
loaded from the A/B inputs. A logic LOW on both of the bus
enable inputs (BUSEN), when clocked through the register,
disables the bus outputs to –2.0V.
The receiver section clocks bus data into the receive
registers after gating with the Receive Enable (RXEN)
input.
All registers are clocked by rising edge of CLK
1
or CLK
2
(or both).
Additional grounding is provided through the ground
pins (GND) which should be connected to 0V. The GND
pins are not electrically connected to the chip.
3-BIT REGISTERED
BUS TRANSCEIVER
Pin
Function
A
0
–A
2
Data Inputs A
B
0
–B
2
Data Inputs B
TEN
1, 2
Transmit Enable Inputs
RXEN
Receive Enable Input
BUSEN
1, 2
Bus Enable Inputs
CLK
1, 2
Clock Inputs
BUS
0
–BUS
2
25
Cutoff Bus Outputs
Q
0
–Q
2
Receive Data Outputs
V
CCO
V
CC
to Output
PIN NAMES
Rev.: G
Issue Date:
Amendment: /0
March 2006
BLOCK DIAGRAM
0
1
D
Q
D
Q
50
25 CUTOFF
0
1
D
Q
D
Q
50
25 CUTOFF
0
1
D
Q
D
Q
50
25 CUTOFF
Q
0
BUS
0
Q
1
BUS
1
Q
2
BUS
2
D
Q
A
0
B
0
A
1
B
1
A
2
B
2
TEN
1
TEN
2
BUSEN
1
BUSEN
2
CLK
1
CLK
2
RXEN
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|---|---|
| SY100E337JZ | 3-BIT SCANNABLE REGISTERED BUS TRANSCEIVER |
| SY100E337JZTR | 3-BIT SCANNABLE REGISTERED BUS TRANSCEIVER |
| SY100E404 | Quad Differential AND/NAND Gate(四差分與門/與非門) |
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相關代理商/技術參數 |
參數描述 |
|---|---|
| SY100E337 | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:3-BIT SCANNABLE REGISTERED BUS TRANSCEIVER |
| SY100E337JC | 功能描述:IC TXRX BUS 3BIT SCAM REG 28PLCC RoHS:否 類別:集成電路 (IC) >> 邏輯 - 緩沖器，驅動器，接收器，收發器 系列:100E 標準包裝:1,000 系列:74ABT 邏輯類型:寄存收發器，非反相 元件數:1 每個元件的位元數:8 輸出電流高，低:32mA，64mA 電源電壓:4.5 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應商設備封裝:24-SOIC 包裝:帶卷 (TR) |
| SY100E337JCTR | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:3-BIT SCANNABLE REGISTERED BUS TRANSCEIVER |
| SY100E337JZ | 功能描述:IC TXRX BUS 3BIT SCAM REG 28PLCC RoHS:是 類別:集成電路 (IC) >> 邏輯 - 緩沖器，驅動器，接收器，收發器 系列:100E 標準包裝:1,000 系列:74ABT 邏輯類型:寄存收發器，非反相 元件數:1 每個元件的位元數:8 輸出電流高，低:32mA，64mA 電源電壓:4.5 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應商設備封裝:24-SOIC 包裝:帶卷 (TR) |
| SY100E337JZ TR | 功能描述:IC TXRX BUS 3BIT SCAM REG 28PLCC RoHS:是 類別:集成電路 (IC) >> 邏輯 - 緩沖器，驅動器，接收器，收發器 系列:100E 標準包裝:1,000 系列:74ABT 邏輯類型:寄存收發器，非反相 元件數:1 每個元件的位元數:8 輸出電流高，低:32mA，64mA 電源電壓:4.5 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應商設備封裝:24-SOIC 包裝:帶卷 (TR) |
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