參數資料
| 型號： | SY100E417JY TR |
| 廠商： | Micrel Inc |
| 文件頁數： | 1/5頁 |
| 文件大小： | 0K |
| 描述： | IC TRANSLATOR QUINT 28-PLCC |
| 標準包裝： | 750 |
| 系列： | 100E |
| 邏輯功能： | 變換器 |
| 位數： | 5 |
| 輸入類型： | LVPECL，PECL |
| 輸出類型： | PECL，LVPECL |
| 通道數： | 5 |
| 輸出/通道數目： | 1 |
| 差分 - 輸入:輸出： | 是/是 |
| 傳輸延遲（最大）： | 0.53ns |
| 電源電壓： | 3 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 28-LCC（J 形引線） |
| 供應商設備封裝： | 28-PLCC |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | SY100E417JYTR SY100E417JYTR-ND |
1
SY100E417
Micrel, Inc.
M9999-032206
hbwhelp@micrel.com or (408) 955-1690
DESCRIPTION
s 3.3V and 5V power supplies required
s Also, supports LVPECL-to-PECL translation
s 500ps propagation delays
s Fully differential design
s Differential line receiver capability
s Available in 28-pin PLCC package
The SY100E417 is a quint LVPECL-to-PECL translator.
It can also be used as a quint PECL-to-LVPECL translator.
The device receives standard PECL signals and translates
them to differential LVPECL output signals (or vice versa).
The SY100E417 can also be used as a differential line
receiver for PECL-to-PECL or LVPECL-to-LVPECL signals.
However, please note that for the latter we will need two
different power supplies. Please refer to Function Table for
more details.
A VBB output is provided for interfacing single ended
input signals. If a single ended input is to be used, the VBB
output should be connected to the Dn input and the active
signal will drive the Dn input. When used, the VBB should
be bypassed to VCC via a 0.01
F capacitor. The VBB is
designed to act as a switching reference for the SY100E417
under single ended input conditions. As a result, the pin
can only source/sink 0.5mA of current.
To accomplish the PECL-to-LVPECL level translation,
the SY100E417 requires three power rails. The VCC and
VCC_VBB supply is to be connected to the standard PECL
supply, the 3.3V supply is to be connected to the VCCO
supply, and GND is connected to the system ground plane.
Both the VCC and VCCO should be bypassed to ground with
a 0.01
F capacitor.
To accomplish the LVPECL-to-PECL level translation,
the SY100E417 requires three power rails as well. The 5.0V
supply is connected to the VCC and VCCO pins, 3.3V supply
is connected to the VCC_VBB pin and GND is connected to
the system ground plane. VCC_VBB is used to provide a
proper VBB output level if a single ended input is used.
VCC_VBB = 3.3V is only required for single-ended LVPECL
input. For differential LVPECL input, VCC_VBB can be either
3.3V or 5.0V.
Under open input conditions, the Dn input will be biased
at a VCC/2 voltage level and the Dn input will be pulled to
GND. This condition will force the "Qn" output low, ensuring
stability.
FEATURES
QUINT LVPECL-TO-PECL
OR PECL-TO-LVPECL
TRANSLATOR
SY100E417
BLOCK DIAGRAM
D0
Q0
D1
Q1
D2
Q2
D3
Q3
D4
Q4
VBB
Function
Vcc
Vcco
Vcc_VBB
PECL-to-LVPECL
5.0V
3.3V
5.0V
LVPECL-to-PECL
5.0V
3.3V
PECL-to-PECL
5.0V
LVPECL-to-LVPECL
5.0V
3.3V
FUNCTION TABLE
Rev.: E
Amendment: /0
Issue Date:
March 2006
Pin
Function
Dn
PECL / LVPECL Inputs
Qn
PECL / LVPECL Outputs
VBB
Reference Voltage Output
VCCO
VCC for Outputs
VCC_VBB
VCC for VBB Output
GND
Common Ground Rail
VCC
VCC for Internal Circuitry
PIN NAMES
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