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參數(shù)資料
型號(hào): SY100E446JZ
廠商: MICREL INC
元件分類(lèi): 通用總線功能
英文描述: 4-BIT PARALLEL-TO-SERIAL CONVERTER
中文描述: 100E SERIES, 4-BIT RIGHT PARALLEL IN SERIAL OUT SHIFT REGISTER, COMPLEMENTARY OUTPUT, PQCC28
封裝: LEAD FREE, PLASTIC, LCC-28
文件頁(yè)數(shù): 1/9頁(yè)
文件大小: 94K
代理商: SY100E446JZ
1
SY10E446
SY10E446
SY100E446
Micrel, Inc.
M9999-032206
hbwhelp@micrel.com or (408) 955-1690
Pin
Function
SIN, SIN
Differential Serial Data Input
D
0
– D
3
Parallel Data Input
SOUT, SOUT
Differential Serial Data Output
CLK, CLK
Differential Clock Input
CL/4, CL/4
Differential 4 Clock Output
CL/8, CL/8
Differential 8 Clock Output
MODE
Conversion Mode, 4-bit/8-bit
SYNC
Conversion Synchronizing Input
V
CCO
V
CC
to Output
DESCRIPTION
FEATURES
I
On-chip clock
÷
4 and
÷
8
I
Extended 100E V
EE
range of –4.2V to –5.5V
I
1.6Gb/s typical data rate capability
I
Differential clock and serial inputs
I
VBB output for single-ended use
I
Asynchronous data synchronization
I
Mode select to expand to 8 bits
I
Internal 75K
input pulldown resistors
I
Fully compatible with Motorola MC10E/100E446
I
Available in 28-pin PLCC package
4-BIT PARALLEL-TO-SERIAL
CONVERTER
The SY10/100E446 are integrated 4-bit parallel-to-
serial data converters. These devices are designed to
operate for NRZ data rates of up to a minimum of 1.3Gb/
s. The chips generate a divide-by-4 and a divide-by-8
clock for both 4-bit conversion and a two-chip 8-bit
conversion function. The conversion sequence was
chosen to convert the parallel data into a serial stream
from bit D
0
to D
3
. A serial input is provided to cascade
two E446 devices for 8-bit conversion applications.
The SYNC input will asynchronously reset the internal
clock circuitry. This pin allows the user to reset the internal
clock conversion unit and, thus, select the start of the
conversion process.
The MODE input is used to select the conversion mode
of the device. With the MODE input LOW (or open) the
device will function as a 4-bit converter. When the mode
input is driven HIGH, the internal load clock will change
on every eighth clock cycle, thus allowing for an 8-bit
conversion scheme using two E446s. When cascaded in
an 8-bit conversion scheme, the devices will not operate
at the 1.3Gb/s data rate of a single device. Refer to the
applications section of this data sheet for more information
on cascading the E446.
For lower data rate applications, a V
BB
reference
voltage is supplied for single-ended inputs. When
operating at clock rates above 500MHz, differential input
signals are recommended. For single-ended inputs, the
V
BB
pin is tied to the inverting differential input and
bypassed via a 0.01
μ
F capacitor. The V
BB
provides the
switching reference for the input differential amplifier. The
V
BB
can also be used to AC couple an input signal.
PIN NAMES
Rev.: F
Issue Date:
Amendment: /0
March 2006
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