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參數資料
| 型號： | SY100EL15L |
| 廠商： | Micrel Semiconductor,Inc. |
| 英文描述： | 3.3V 1:4 CLOCK DISTRIBUTION |
| 中文描述： | 3.3V的1:4時鐘分配 |
| 文件頁數： | 1/4頁 |
| 文件大小： | 53K |
| 代理商： | SY100EL15L |
1
ClockWorks
ClockWorks
SY100EL15L
Micrel
The SY100EL15L is a low skew 1:4 clock distribution
IC designed explicitly for low skew clock distribution
applications. The device can be driven by either a
differential or single-ended ECL or, if positive power
supplies are used, PECL input signal. If a single-ended
input is to be used the V
BB
output should be connected
to the CLK input and bypassed to ground via a 0.01
μ
F
capacitor. The V
BB
output is designed to act as the
switching reference for the input of the EL15 under single-
ended input conditions. As a result, this pin can only
source/sink up to 0.5mA of current.
The EL15 features a multiplexed clock input to allow
for the distribution of a lower speed scan or test clock
along with the high speed system clock. When LOW (or
left open and pulled LOW by the input pull-down resistor)
the SEL pin will select the differential clock input.
The common enable (EN) is synchronous so that the
outputs will only be enabled/disabled when they are
already in the LOW state. This avoids any chance of
generating a runt clock pulse when the device is enabled/
disabled as can happen with an asynchronous control.
The internal flip flop is clocked on the falling edge of the
input clock, therefore all associated specification limits
are referenced to the negative edge of the clock input.
When both differential inputs are left open, CLK input
will pull down to V
EE
and CLK input will bias around
V
CC
/2.
Pin
Function
CLK
Differential Clock Inputs
SCLK
Synchronous Clock Input
EN
Synchronous Enable
SEL
Clock Select Input
V
BB
Reference Output
Q
0-3
Differential Clock Outputs
TRUTH TABLE
PIN NAMES
FEATURES
DESCRIPTION
1999 Micrel
Rev.: A
Issue Date: December 1999
Amendment: /0
PIN CONFIGURATION/BLOCK DIAGRAM
CLK
SCLK
SEL
EN
Q
L
X
L
L
L
H
X
L
L
H
X
L
H
L
L
X
H
H
L
H
X
X
X
H
L*
* On next negative transition of CLK or SCLK
V
CC
16
CLK
13
Q
0
Q
0
Q
1
Q
2
Q
2
Q
3
Q
3
V
EE
9
SEL
10
V
BB
11
CLK
12
EN
15
14
Q
1
1
2
3
4
5
6
7
8
D
Q
1 0
SCLK
SOIC
TOP VIEW
I
3.3V power supply
I
50ps output-to-output skew
I
Low power
I
Synchronous enable/disable
I
Multiplexed clock input
I
75K
internal input pull-down resistors
I
ESD protection of 2000V
I
Available in 16-pin SOIC package
3.3V 1:4 CLOCK
DISTRIBUTION
Synergy
High-Speed Products
相關PDF資料 |
PDF描述 |
|---|---|
| SY100EL15LZC | 3.3V 1:4 CLOCK DISTRIBUTION |
| SY100EL15LZCTR | 3.3V 1:4 CLOCK DISTRIBUTION |
| SY100EL16VSKCTR | 5V/3.3V VARIABLE OUTPUT SWING DIFFERENTIAL RECEIVER |
| SY100EL16VSKG | 5V/3.3V VARIABLE OUTPUT SWING DIFFERENTIAL RECEIVER |
| SY100EL16VSKGTR | 5V/3.3V VARIABLE OUTPUT SWING DIFFERENTIAL RECEIVER |
相關代理商/技術參數 |
參數描述 |
|---|---|
| SY100EL15L_06 | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:3.3V 1:4 CLOCK DISTRIBUTION |
| SY100EL15LZC | 功能描述:IC CLOCK BUFFER MUX 2:4 16-SOIC RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘緩沖器，驅動器 系列:100EL, Precision Edge® 標準包裝:1 系列:HiPerClockS™ 類型:扇出緩沖器（分配），多路復用器 電路數:1 比率 - 輸入:輸出:2:18 差分 - 輸入:輸出:是/無 輸入:CML，LVCMOS，LVPECL，LVTTL，SSTL 輸出:LVCMOS，LVTTL 頻率 - 最大:250MHz 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:32-LQFP 供應商設備封裝:32-TQFP（7x7） 包裝:- 其它名稱:800-1923-6 |
| SY100EL15LZC TR | 功能描述:IC CLOCK BUFFER MUX 2:4 16-SOIC RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘緩沖器，驅動器 系列:100EL, Precision Edge® 標準包裝:1 系列:HiPerClockS™ 類型:扇出緩沖器（分配），多路復用器 電路數:1 比率 - 輸入:輸出:2:18 差分 - 輸入:輸出:是/無 輸入:CML，LVCMOS，LVPECL，LVTTL，SSTL 輸出:LVCMOS，LVTTL 頻率 - 最大:250MHz 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:32-LQFP 供應商設備封裝:32-TQFP（7x7） 包裝:- 其它名稱:800-1923-6 |
| SY100EL15LZCTR | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:3.3V 1:4 CLOCK DISTRIBUTION |
| SY100EL15LZG | 功能描述:時鐘驅動器及分配 3.3V 1:4 Clock Distribution (I Temp, Green) RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
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