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參數資料
| 型號： | SY100EL34LZC |
| 廠商： | MICREL INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 5V/3.3V ±2, ±4, ±8 CLOCK GENERATION CHIP |
| 中文描述： | 100EL SERIES, LOW SKEW CLOCK DRIVER, 3 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16 |
| 封裝： | 0.150 INCH, SOIC-16 |
| 文件頁數： | 1/4頁 |
| 文件大小： | 57K |
| 代理商： | SY100EL34LZC |
The SY10/100EL34/L are low skew
÷
2,
÷
4,
÷
8 clock
generation chips designed explicitly for low skew clock
generation applications. The internal dividers are
synchronous to each other, therefore, the common output
edges are all precisely aligned. The devices can be driven
by either a differential or single-ended ECL or, if positive
power supplies are used, PECL input signal. In addition,
by using the V
BB
output, a sinusoidal source can be AC-
coupled into the device. If a single-ended input is to be
used, the V
BB
output should be connected to the CLK
input and bypassed to ground via a 0.01
μ
F capacitor.
The V
BB
output is designed to act as the switching
reference for the input of the EL34/L under single-ended
input conditions. As a result, this pin can only source/
sink up to 0.5mA of current.
The common enable (EN) is synchronous so that the
internal dividers will only be enabled/disabled when the
internal clock is already in the LOW state. This avoids
any chance of generating a runt clock pulse on the
internal clock when the device is enabled/disabled as
can happen with an asynchronous control. An internal
runt pulse could lead to losing synchronization between
the internal divider stages. The internal enable flip-flop is
clocked on the falling edge of the divider stages. The
internal enable flip-flop is clocked on the falling edge of
the input clock, therefore, all associated specification
limits are referenced to the negative edge of the clock
input.
Upon start-up, the internal flip-flops will attain a random
state; the master reset (MR) input allows for the
synchronization of the internal dividers, as well as for
multiple EL34/Ls in a system.
Pin
Function
CLK
Differential Clock Inputs
EN
Synchronous Enable
MR
Master Reset
V
BB
Reference Output
Q
0
Differential
÷
2 Outputs
Differential
÷
4 Outputs
Differential
÷
8 Outputs
Q
1
Q
2
DESCRIPTION
PIN NAMES
FEATURES
Rev.: F
Issue Date:
Amendment: /0
August, 1998
5V/3.3V
÷
2,
÷
4,
÷
8 CLOCK
GENERATION CHIP
ClockWorks
SY10EL34/L
SY100EL34/L
PIN CONFIGURATION/BLOCK DIAGRAM
SOIC
TOP VIEW
I
3.3V and 5V power supply options
I
50ps output-to-output skew
I
Synchronous enable/disable
I
Master Reset for synchronization
I
Internal 75K
input pull-down resistors
I
Available in 16-pin SOIC package
V
CC
EN
NC
CLK
CLK
V
BB
MR
V
EE
Q
0
Q
0
V
CC
Q
1
Q
1
V
CC
Q
2
Q
2
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
R
Q
÷2
Q
R
÷4
Q
÷8
R
Q D
R
1
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相關代理商/技術參數 |
參數描述 |
|---|---|
| SY100EL34LZC TR | 功能描述:IC CLK GEN /2/4/6 5V/3.3V 16SOIC RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發生器，PLL，頻率合成器 系列:100EL, Precision Edge® 標準包裝:27 系列:Precision Edge® 類型:頻率合成器 PLL:是 輸入:PECL，晶體 輸出:PECL 電路數:1 比率 - 輸入:輸出:1:1 差分 - 輸入:輸出:無/是 頻率 - 最大:800MHz 除法器/乘法器:是/無 電源電壓:3.135 V ~ 5.25 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:28-SOIC（0.295"，7.50mm 寬） 供應商設備封裝:28-SOIC 包裝:管件 |
| SY100EL34LZCTR | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:5V/3.3V ±2, ±4, ±8 CLOCK GENERATION CHIP |
| SY100EL34LZG | 功能描述:時鐘發生器及支持產品 3.3V /2, /4. /8 Clock Generation Chip (I Temp, Green) RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
| SY100EL34LZG TR | 功能描述:時鐘發生器及支持產品 3.3V /2, /4, /8 Clock Generation Chip (I Temp, Green) RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
| SY100EL34LZGTR | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:5V/3.3V ÷2, ÷4, ÷8 Clock Generation Chip |
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