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參數資料
| 型號： | SY100EPT21LZCTR |
| 廠商： | MICREL INC |
| 元件分類： | 通用總線功能 |
| 英文描述： | 3.3V DIFFERENTIAL LVPECL-to-LVTTL TRANSLATOR |
| 中文描述： | PECL TO TTL TRANSLATOR, TRUE OUTPUT, PDSO8 |
| 封裝： | PLASTIC, SOIC-8 |
| 文件頁數： | 1/8頁 |
| 文件大小： | 87K |
| 代理商： | SY100EPT21LZCTR |
Pin
Function
Q
LVTTL Output
D, /D
Differential LVPECL Input Pair
V
CC
V
BB
GND
Positive Supply
Output Reference Voltage
Ground
DESCRIPTION
I
3.3V power supply
I
1.9ns typical propagation delay
I
275MHz f
MAX
(Clock bit stream, not pseudo-random)
I
Differential LVPECL inputs
I
24mA LVTTL outputs
I
Flow-through pinouts
I
Internal input resistors: pulldown on D, pulldown
and pullup on /D
I
Q output will default LOW with inputs open or at
GND
I
V
BB
output
I
Available in 8-pin MSOP and SOIC package
The SY100EPT21L is a single differential LVPECL-to-
LVTTL translator using a single +3.3V power supply.
Because LVPECL (Low Voltage Positive ECL) levels are
used, only +3.3V and ground are required. The small
outline 8-lead SOIC package and low skew single gate
design make the EPT21L ideal for applications that
require the translation of a clock or data signal where
minimal space, low power, and low cost are critical.
V
BB
allows a differential, single-ended, or AC-coupled
interface to the device. If used, the V
BB
output should be
bypassed to V
CC
with 0.01
μ
F capacitor.
Under open input conditions, the /D will be biased at a
V
CC
/2 voltage level and the D input will be pulled to
ground. This condition will force the Q output low to
provide added stability.
The 100EPT is compatible with positive ECL 100K
logic levels.
FEATURES
3.3V DIFFERENTIAL
LVPECL-to-LVTTL
TRANSLATOR
PIN NAMES
PIN CONFIGURATION/BLOCK DIAGRAM
(Available in 8-pin SOIC and 8-pin MSOP)
SY100EPT21L
1
NC
D
D
V
BB
8
V
CC
Q
NC
GND
7
6
5
2
3
4
LVPECL
LVTTL
1
Rev.: A
Issue Date:
Amendment: /1
July 2000
相關PDF資料 |
PDF描述 |
|---|---|
| SY100EPT21L | 210V 80A TSPD; Package: SMB; No of Pins: 2; Container: Tape and Reel; Qty per Container: 2500 |
| SY100EPT21LKC | 3.3V DIFFERENTIAL LVPECL-to-LVTTL TRANSLATOR |
| SY100EPT21LKCTR | 3.3V DIFFERENTIAL LVPECL-to-LVTTL TRANSLATOR |
| SY100EPT21LZC | 3.3V DIFFERENTIAL LVPECL-to-LVTTL TRANSLATOR |
| SY100EPT23LZCTR | 3.3V DUAL DIFFERENTIAL LVPECL-to-LVTTL TRANSLATOR |
相關代理商/技術參數 |
參數描述 |
|---|---|
| SY100EPT21LZG | 功能描述:轉換 - 電壓電平 3.3V Differential LVPECL-to-LVTTL Translator (I Temp, Green) RoHS:否 制造商:Micrel 類型:CML/LVDS/LVPECL to LVCMOS/LVTTL 傳播延遲時間:1.9 ns 電源電流:14 mA 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:MLF-8 |
| SY100EPT21LZG TR | 功能描述:轉換 - 電壓電平 3.3V Differential LVPECL-to-LVTTL Translator (I Temp, Green) RoHS:否 制造商:Micrel 類型:CML/LVDS/LVPECL to LVCMOS/LVTTL 傳播延遲時間:1.9 ns 電源電流:14 mA 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:MLF-8 |
| SY100EPT21LZI | 功能描述:IC TRANSLATOR DIFF 3.3V 8-SOIC RoHS:否 類別:集成電路 (IC) >> 邏輯 - 變換器 系列:100EPT 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:100 系列:- 邏輯功能:變換器，雙向 位數:2 輸入類型:CMOS 輸出類型:CMOS 數據速率:16Mbps 通道數:2 輸出/通道數目:1 差分 - 輸入:輸出:無/無 傳輸延遲（最大）:15ns 電源電壓:1.65 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:10-UFQFN 供應商設備封裝:10-UTQFN（1.4x1.8） 包裝:管件 |
| SY100EPT21LZI TR | 功能描述:IC TRANSLATOR DIFF 3.3V 8-SOIC RoHS:否 類別:集成電路 (IC) >> 邏輯 - 變換器 系列:100EPT 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:100 系列:- 邏輯功能:變換器，雙向 位數:2 輸入類型:CMOS 輸出類型:CMOS 數據速率:16Mbps 通道數:2 輸出/通道數目:1 差分 - 輸入:輸出:無/無 傳輸延遲（最大）:15ns 電源電壓:1.65 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:10-UFQFN 供應商設備封裝:10-UTQFN（1.4x1.8） 包裝:管件 |
| SY100EPT22VKC | 功能描述:IC XLATOR LV TTL/CMOS-PECL 8MSOP RoHS:是 類別:集成電路 (IC) >> 邏輯 - 變換器 系列:100EPT 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:100 系列:- 邏輯功能:變換器，雙向 位數:2 輸入類型:CMOS 輸出類型:CMOS 數據速率:16Mbps 通道數:2 輸出/通道數目:1 差分 - 輸入:輸出:無/無 傳輸延遲（最大）:15ns 電源電壓:1.65 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:10-UFQFN 供應商設備封裝:10-UTQFN（1.4x1.8） 包裝:管件 |
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