參數資料
| 型號： | SY100S313JZ TR |
| 廠商： | Micrel Inc |
| 文件頁數： | 1/4頁 |
| 文件大小： | 0K |
| 描述： | IC BUFF/DVR 4BIT N-INVERT 28PLCC |
| 標準包裝： | 750 |
| 系列： | 100S |
| 邏輯類型： | 緩沖器/線路驅動器，非反相 |
| 元件數： | 1 |
| 每個元件的位元數： | 4 |
| 電源電壓： | 4.2 V ~ 5.5 V |
| 工作溫度： | 0°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-LCC（J 形引線） |
| 供應商設備封裝： | 28-PLCC |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | SY100S313JZTR SY100S313JZTR-ND |
SY54020AR
Low Voltage 1.2V/1.8V/2.5V CML 1:4 Fanout
Buffer with /EN 3.2Gbps, 3.2GHz
Precision Edge is a registered trademark of Micrel, Inc.
MLF and MicroLeadFrame are registered trademarks of Amkor Technology.
Micrel Inc. 2180 Fortune Drive San Jose, CA 95131 USA tel +1 (408) 944-0800 fax + 1 (408) 474-1000 http://www.micrel.com
April 2009
M9999-041409-A
hbwhelp@micrel.com or (408) 955-1690
General Description
The SY54020AR is a fully differential, low voltage
1.2V/1.8V/2.5V CML 1:4 Fanout Buffer with active-low
Enable (/EN). The Enable is synchronous so that the
outputs will only be enabled/disabled when they are
already in the LOW state. This avoids any chance of
generating a runt clock pulse when the device is
enabled/disabled as can happen with an asynchronous
control. When this device is used as a clock fanout,
disabling the downstream clock may reduce system
power. The SY54020AR can process clock signals as
fast as 3.2 GHz or data patterns up to 3.2Gbps.
The differential input includes Micrel’s unique, 3-pin
input termination architecture that interfaces to LVPECL,
LVDS or CML differential signals as small as 100mV
(200mVpp) without any level-shifting or termination
resistor networks in the signal path. For AC-coupled
input
interface
applications,
an
internal
voltage
reference is provided to bias the VT pin. The outputs are
CML, with extremely fast rise/fall times guaranteed to be
less than 100ps.
The SY54020AR operates from a 2.5V ±5% core supply
and a 1.2V, 1.8V or 2.5V ±5% output supply and is
guaranteed over the full industrial temperature range (–
40°C to +85°C).
Datasheets and support documentation can be found on
Micrel’s web site at: www.micrel.com.
Functional Block Diagram
Precision Edge
Features
1.2V/1.8V/2.5V CML 1:4 Fanout Buffer
Active-low Enable (/EN) input to disable the outputs
Guaranteed AC performance over temperature and
voltage:
– DC-to > 3.2Gbps Data throughput
– DC-to > 3.2GHz Clock throughput
– <320 ps propagation delay (IN-to-Q)
– <20ps within-device skew
– <100 ps rise/fall times
Ultra-low jitter design
– <1psRMS cycle-to-cycle jitter
High-speed CML outputs
2.5V ±5% V
CC , 1.2/1.8V/2.5V ±5% VCCO power supply
operation
Industrial temperature range: –40°C to +85°C
Available in 16-pin (3mm x 3mm) MLF package
Applications
SONET clock and data distribution
Fibre Channel clock and data distribution
Gigabit Ethernet clock and data distribution
Markets
Storage
ATE
Test and measurement
Enterprise networking equipment
High-end servers
Access
Metro area network equipment
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| SY100S314JZ | 功能描述:緩沖器和線路驅動器 Quint Differential Line Receiver (Lead Free) RoHS:否 制造商:Micrel 輸入線路數量:1 輸出線路數量:2 極性:Non-Inverting 電源電壓-最大:+/- 5.5 V 電源電壓-最小:+/- 2.37 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:MSOP-8 封裝:Reel |
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