參數資料
| 型號： | SY100S811ZH TR |
| 廠商： | Micrel Inc |
| 文件頁數： | 1/4頁 |
| 文件大小： | 0K |
| 描述： | IC CLK FANOUT BUFFER 2:9 28-SOIC |
| 標準包裝： | 1,000 |
| 系列： | Precision Edge® |
| 類型： | 扇出緩沖器（分配） |
| 電路數： | 1 |
| 比率 - 輸入:輸出： | 2:9 |
| 差分 - 輸入:輸出： | 是/是 |
| 輸入： | PECL，TTL |
| 輸出： | PECL |
| 電源電壓： | 4.75 V ~ 5.25 V |
| 工作溫度： | 0°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-SOIC（0.295"，7.50mm 寬） |
| 供應商設備封裝： | 28-SOIC |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | SY100S811ZHTR SY100S811ZHTR-ND |
1
Micrel, Inc.
M9999-021407
hbwhelp@micrel.com or (408) 955-1690
Precision Edge
SY100S811
FEATURES
DESCRIPTION
Precision Edge
SY100S811
Rev.: H
Amendment: /0
Issue Date:
February 2007
SINGLE SUPPLY 1:9
PECL/TTL-TO-PECL
s PECL version of popular ECLinPS E111
s Low skew
s Guaranteed skew spec
s VBB output
s TTL enable input
s Selectable TTL or PECL clock input
s Single +5V supply
s Differential internal design
s Similar pin configuration to E111
s PECL I/O fully compatible with industry standard
s Internal 75K
PECL input pull-down resistors
s Available in 28-pin PLCC and SOIC packages
The SY100S811 is a low skew 1-to-9 PECL differential
driver designed for clock distribution in new, high-
performance PECL systems. It accepts either a PECL
clock input or a TTL input by using the TTL enable pin TEN.
When the TTL enable pin is HIGH, the TTL input is enabled
and the PECL input is disabled. When the enable pin is set
LOW, the TTL input is disabled and the PECL input is
enabled.
The device is specifically designed and produced for low
skew. The interconnect scheme and metal layout are
carefully optimized for minimal gate-to-gate skew within
the device. Wafer characterization and process control
ensure consistent distribution of propagation delay from lot
to lot. Since the S811 shares a common set of “basic”
processing with the other members of the ECLinPS family,
wafer characterization at the point of device personalization
allows for tighter control of parameters, including
propagation delay.
To ensure that the skew specification is met, it is
necessary that both sides of the differential output are
terminated into 50
, even if only one side is being used. ln
most applications, all nine differential pairs will be used
and, therefore, terminated. In the case where fewer than
nine pairs are used, it is necessary to terminate at least the
output pairs on the same package side (i.e. sharing the
same VCCO as the pair(s) being used on that side) in order
to maintain minimum skew.
The VBB output is intended for use as a reference
voltage for single-ended reception of PECL signals to that
device only. When using VBB for this purpose, it is
recommended that VBB is decoupled to VCC via a 0.01
F
capacitor.
BLOCK DIAGRAM
VBB
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
EIN
0
1
TIN
TEN
Precision Edge is a registered trademark of Micrel, Inc.
Precision Edge
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