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參數(shù)資料
| 型號(hào)： | SY100S815 |
| 廠商： | Micrel Semiconductor,Inc. |
| 英文描述： | Single Supply Quad PECL/TTL-to-PECL(單電源低斜移4選1 PECL差分驅(qū)動(dòng)器) |
| 中文描述： | 單電源四路PECL / TTL電到PECL的（單電源低斜移4選1 PECL的差分驅(qū)動(dòng)器） |
| 文件頁(yè)數(shù)： | 1/4頁(yè) |
| 文件大小： | 67K |
| 代理商： | SY100S815 |
BLOCK DIAGRAM
FEATURES
DESCRIPTION
Rev.: F
Issue Date: October, 1998
Amendment: /0
The SY100S815 is a low skew 1-to-4 PECL differential
driver designed for clock distribution in new, high-
performance PECL systems. It accepts either a PECL
clock input or a TTL input by using the TTL enable pin T
EN
.
When the TTL enable pin is HIGH, the TTL input is enabled
and the PECL input is disabled. When the enable pin is set
LOW, the TTL input is disabled and the PECL input is
enabled.
The device is specifically designed and produced for low
skew. The interconnect scheme and metal layout are
carefully optimized for minimal gate-to-gate skew within
the device. Wafer characterization and process control
ensure consistent distribution of propagation delay from lot
to lot. Since the S815 shares a common set of “basic”
processing with the other members of the ECLinPS family,
wafer characterization at the point of device personalization
allows for tighter control of parameters, including
propagation delay.
To ensure that the skew specification is met, it is
necessary that both sides of the differential output are
terminated into 50
, even if only one side is being used. In
most applications, all nine differential pairs will be used
and, therefore, terminated. In the case where fewer than
nine pairs are used, it is necessary to terminate at least the
output pairs on the same package side (i.e. sharing the
same V
CCO
as the pair(s) being used on that side) in order
to maintain minimum skew.
I
Quad PECL version of popular ECLinPS E111
I
Low skew
I
Guaranteed skew spec
I
TTL enable input
I
Selectable TTL or PECL clock input
I
Single +5V supply
I
Differential internal design
I
PECL I/O fully compatible with industry standard
I
Internal 75k
PECL input pull-down resistors
I
Available in 16-pin SOIC package
ClockWorks
SY100S815
SINGLE SUPPLY QUAD
PECL/TTL-TO-PECL
Pin
Function
E
IN
, E
IN
Differential PECL Input Pair
T
IN
TTL Input
T
EN
TTL Input Enable
Q
0
, Q
0
– Q
3
, Q
3
Differential PECL Outputs
V
CC
PECL V
CC
(+5.0V)
V
EE
PECL Ground (0V)
PIN CONFIGURATION
PIN NAMES
1
2
3
4
5
6
7
8
15
16
14
13
12
11
10
9
V
CC
T
IN
Q
3
Q
2
Q
2
V
CCO
E
IN
T
EN
V
EE
Q
0
Q
0
Q
1
V
CCO
TOP VIEW
SOIC
Z16-1
Q
3
E
IN
Q
1
Q
0
Q
0
Q
1
Q
1
Q
2
Q
2
Q
3
Q
3
E
IN
E
IN
0
1
T
IN
T
EN
1
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| SY100S815ZC | 功能描述:IC DRIVER DIFF 1:4 SGL 16-SOIC RoHS:否 類別:集成電路 (IC) >> 邏輯 - 專用邏輯 系列:100S 產(chǎn)品變化通告:Product Discontinuation 25/Apr/2012 標(biāo)準(zhǔn)包裝:1,500 系列:74SSTV 邏輯類型:DDR 的寄存緩沖器 電源電壓:2.3 V ~ 2.7 V 位數(shù):14 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:48-TFSOP（0.240"，6.10mm 寬） 供應(yīng)商設(shè)備封裝:48-TSSOP 包裝:帶卷 (TR) |
| SY100S815ZC TR | 功能描述:IC DRIVER DIFF 1:4 SGL 16-SOIC RoHS:否 類別:集成電路 (IC) >> 邏輯 - 專用邏輯 系列:100S 產(chǎn)品變化通告:Product Discontinuation 25/Apr/2012 標(biāo)準(zhǔn)包裝:1,500 系列:74SSTV 邏輯類型:DDR 的寄存緩沖器 電源電壓:2.3 V ~ 2.7 V 位數(shù):14 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:48-TFSOP（0.240"，6.10mm 寬） 供應(yīng)商設(shè)備封裝:48-TSSOP 包裝:帶卷 (TR) |
| SY100S815ZH | 功能描述:轉(zhuǎn)換 - 電壓電平 Single Supply Quad PECL/TTL-to-PECL (Green) RoHS:否 制造商:Micrel 類型:CML/LVDS/LVPECL to LVCMOS/LVTTL 傳播延遲時(shí)間:1.9 ns 電源電流:14 mA 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MLF-8 |
| SY100S815ZH TR | 功能描述:轉(zhuǎn)換 - 電壓電平 Single Supply Quad PECL/TTL-to-PECL (Green) RoHS:否 制造商:Micrel 類型:CML/LVDS/LVPECL to LVCMOS/LVTTL 傳播延遲時(shí)間:1.9 ns 電源電流:14 mA 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MLF-8 |
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