參數資料
| 型號： | SY100S838LZC |
| 廠商： | Micrel Inc |
| 文件頁數： | 1/5頁 |
| 文件大小： | 0K |
| 描述： | IC CLOCK GEN 3.3V/5V 20-SOIC |
| 標準包裝： | 38 |
| 系列： | Precision Edge® |
| 類型： | 時鐘發生器 |
| PLL： | 無 |
| 輸入： | ECL，PECL |
| 輸出： | 時鐘 |
| 電路數： | 1 |
| 比率 - 輸入:輸出： | 1:4 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 1GHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3 V ~ 3.8 V |
| 工作溫度： | 0°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-SOIC（0.295"，7.50mm 寬） |
| 供應商設備封裝： | 20-SOIC（寬型） |
| 包裝： | 管件 |
1
Precision Edge
SY100S838
SY100S838L
Micrel, Inc.
M9999-113006
hbwhelp@micrel.com or (408) 955-1690
The SY100S838/L is a low skew (÷1, ÷2/3) or (÷2, ÷4/
6) clock generation chip designed explicitly for low skew
clock generation applications. The internal dividers are
synchronous to each other, therefore, the common output
edges are all precisely aligned. The devices can be driven
by either a differential or single-ended ECL or, if positive
power supplies are used, PECL input signal. In addition,
by using the VBB output, a sinusoidal source can be AC-
coupled into the device. If a single-ended input is to be
used, the VBB output should be connected to the CLK
input and bypassed to ground via a 0.01F capacitor.
The VBB output is designed to act as the switching
reference for the input of the SY100S838/L under single-
ended input conditions. As a result, this pin can only
source/sink up to 0.5mA of current.
The Function Select (FSEL) input is used to determine
what clock generation chip function is. When FSEL input
is LOW, SY100S838/L functions as a divide by 2 and by
4/6 clock generation chip. However, if FSEL input is HIGH,
it functions as a divide by 1 and by 2/3 clock chip.
The common enable (EN) is synchronous so that the
internal dividers will only be enabled/disabled when the
internal clock is already in the LOW state. This avoids
any chance of generating a runt clock pulse on the
internal clock when the device is enabled/disabled as
can happen with an asynchronous control. An internal
runt pulse could lead to losing synchronization between
the internal divider stages. The internal enable flip-flop is
clocked on the falling edge of the input clock, therefore,
all associated specification limits are referenced to the
negative edge of the clock input.
Upon start-up, the internal flip-flops will attain a random
state; the master reset (MR) input allows for the
synchronization of the internal dividers, as well as for
multiple SY100S838/Ls in a system.
■ 3.3V and 5V power supply options
■ 50ps output-to-output skew
■ Synchronous enable/disable
■ Master Reset for synchronization
■ Internal 75K input pull-down resistors
■ Available in 20-pin SOIC package
DESCRIPTION
FEATURES
Rev.: G
Amendment: /0
Issue Date:
November 2006
(
÷1, ÷2/3) OR (÷2, ÷4/6)
CLOCK GENERATION CHIP
Precision Edge
SY100S838
SY100S838L
Pin
Function
CLK
Differential Clock Inputs
FSEL
Function Select Input
EN
Synchronous Enable
MR
Master Reset
VBB
Reference Output
Q0, Q1
Differential ÷1 or ÷2 Outputs
Q2, Q3
Differential ÷2/3 or ÷4/6 Outputs
DIVSEL
Frequency Select Input
PIN NAMES
FSEL
DIVSEL
Q0, Q1 OUTPUTS
Q2, Q3 OUTPUTS
LL
Divide by 2
Divide by 4
LH
Divide by 2
Divide by 6
HL
Divide by 1
Divide by 2
HH
Divide by 1
Divide by 3
CLK
EN
MR
Function
ZL
L
Divide
ZZ
H
L
Hold Q0–3
XX
H
Reset Q0–3
TRUTH TABLE
NOTES:
Z = LOW-to-HIGH transition
ZZ = HIGH-to-LOW transition
Precision Edge is a registered trademark of Micrel, Inc.
Precision Edge
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相關代理商/技術參數 |
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|---|---|
| SY100S838LZC TR | 制造商:Micrel Inc 功能描述:Micrel SY100S838LZC TR, Clock Divider 1GHz 2 / 4 General Purpose 3.3V-5V 20-Pin SOIC W T/R |
| SY100S838LZG | 功能描述:時鐘發生器及支持產品 3.3V (/1, /2-3) or (/2, /4-6) Clock Generation Chip (I Temp, Green) RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
| SY100S838LZG TR | 功能描述:時鐘發生器及支持產品 3.3V (/1, /2-3) or (/2, /4-6) Clock Generation Chip (I Temp, Green) RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
| SY100S838LZI | 功能描述:IC CLOCK GEN 3.3V/5V 20-SOIC RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發生器，PLL，頻率合成器 系列:Precision Edge® 標準包裝:27 系列:Precision Edge® 類型:頻率合成器 PLL:是 輸入:PECL，晶體 輸出:PECL 電路數:1 比率 - 輸入:輸出:1:1 差分 - 輸入:輸出:無/是 頻率 - 最大:800MHz 除法器/乘法器:是/無 電源電壓:3.135 V ~ 5.25 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:28-SOIC（0.295"，7.50mm 寬） 供應商設備封裝:28-SOIC 包裝:管件 |
| SY100S838LZI TR | 功能描述:IC CLOCK GEN 3.3V/5V 20-SOIC RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發生器，PLL，頻率合成器 系列:Precision Edge® 標準包裝:27 系列:Precision Edge® 類型:頻率合成器 PLL:是 輸入:PECL，晶體 輸出:PECL 電路數:1 比率 - 輸入:輸出:1:1 差分 - 輸入:輸出:無/是 頻率 - 最大:800MHz 除法器/乘法器:是/無 電源電壓:3.135 V ~ 5.25 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:28-SOIC（0.295"，7.50mm 寬） 供應商設備封裝:28-SOIC 包裝:管件 |
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