參數資料
| 型號： | SY100S891JC |
| 廠商： | Micrel Inc |
| 文件頁數： | 1/4頁 |
| 文件大小： | 0K |
| 描述： | IC REGISTERED TRANSCVR 5B 28PLCC |
| 標準包裝： | 38 |
| 系列： | 100S |
| 邏輯類型： | 寄存收發器，非反相 |
| 元件數： | 1 |
| 每個元件的位元數： | 5 |
| 電源電壓： | 4.2 V ~ 5.5 V |
| 工作溫度： | 0°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-LCC（J 形引線） |
| 供應商設備封裝： | 28-PLCC |
| 包裝： | 管件 |
1
SY100S891
Micrel, Inc.
M9999-032406
hbwhelp@micrel.com or (408) 955-1690
Pin
Function
BUSEN0–4
Bus Enable Inputs
D0 – D4
Data Inputs
CLK1
Bus Driver Clock Input
CLK2
Receive Register Clock
MR
Master Reset
Q0 – Q4
Bus Receive Outputs
BUS0–4
Bus Outputs
DESCRIPTION
FEATURES
s 25
cut-off bus outputs
s 50
receiver outputs
s Transmit and receive registers with separate clocks
s 1500ps max. delay from CLK1 to Bus Outputs (BUS)
s 1500ps max. delay from CLK2 to Receiver Outputs (Q)
s Individual bus enable pins
s Internal 75K
input pull-down resistors
s Voltage and temperature compensation for improved
noise immunity
s Industry standard 100K ECL levels
s Extended supply voltage option:
VEE = –4.2V to –5.5V
s Available in 28-pin PLCC package
The SY100S891 is a 5-bit registered transceiver
containing five bus transceivers with both transmit and
receive registers. The bus outputs (BUS0 – BUS4) are
specified for driving a 25 ohm bus and the receive outputs
(Q0 – Q4) are specified for driving a 50 ohm line. The
bus outputs have a normal high level output voltage and
a normal low level output voltage when the bus enable
(BUSEN0 – BUSEN4) is high. However, the output is
switched to a cut-off level when a bus-enable is low.
This cut-off level is sufficiently low that a relatively high
impedance is presented to the bus in order to minimize
reflections. There is one bus-enable for each bus driver;
a clock (CLK1) which is common to all five bus driver
registers; and a separate clock (CLK2) which is common
to all five receive registers. Data at the D inputs is clocked
to the Bus register by a positive transition of CLK1 and
data on the bus is clocked into the Receiver register by
a positive transition of CLK2. A high on the Master Reset
clears all registers.
5-BIT REGISTERED
TRANSCEIVER
PIN NAMES
SY100S891
Rev.: F
Amendment: /0
Issue Date:
March 2006
相關PDF資料 |
PDF描述 |
|---|---|
| SY10E101JI TR | IC GATE OR/NO QUAD 4INPUT 28PLCC |
| SY10E104JI TR | IC GATE AND/NAND QUINT 28-PLCC |
| SY10E107JC TR | IC GATE XOR/XNOR QUINT 28-PLCC |
| SY10E111JI TR | IC CLK FANOUT BUFFER 1:9 28-PLCC |
| SY10E111LEJC TR | IC CLK FANOUT BUFFER 1:9 28-PLCC |
相關代理商/技術參數 |
參數描述 |
|---|---|
| SY100S891JZ | 功能描述:寄存器 5-bit Registered Transceiver (Lead Free) RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數量:1 最大時鐘頻率:36 MHz 傳播延遲時間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube |
| SY100S891JZ TR | 功能描述:寄存器 5-bit Registered Transceiver (Lead Free) RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數量:1 最大時鐘頻率:36 MHz 傳播延遲時間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube |
| SY107M050AG3AAKPLP | 制造商:KEMET Corporation 功能描述:CAP ALUM 100UF -40+105?C 3000H 8 X 11 RC 0 73 ARMS RDL - Bulk |
| SY108M010AH2EAKPLP | 制造商:KEMET Corporation 功能描述:CAP ALUM 1000UF -40+105?C 4000H 10 X 16 RC 1 43 ARMS RDL - Ammo Pack |
| SY10E016JC | 功能描述:IC UPCOUNTER 8BIT SYNC 28-PLCC RoHS:否 類別:集成電路 (IC) >> 邏輯 -計數器，除法器 系列:10E 產品變化通告:1Q2012 Discontinuation 30/Mar/2012 標準包裝:2,500 系列:74HC 邏輯類型:二進制計數器 方向:上 元件數:1 每個元件的位元數:12 復位:異步 計時:- 計數速率:50MHz 觸發器類型:負邊沿 電源電壓:2 V ~ 6 V 工作溫度:-55°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:16-TSSOP 包裝:帶卷 (TR) |
發布緊急采購，3分鐘左右您將得到回復。