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參數資料
| 型號： | SY10E195JC |
| 廠商： | MICREL INC |
| 元件分類： | 通用總線功能 |
| 英文描述： | PROGRAMMABLE DELAY CHIP |
| 中文描述： | SILICON DELAY LINE, COMPLEMENTARY OUTPUT, PQCC28 |
| 封裝： | PLASTIC, LCC-28 |
| 文件頁數： | 1/8頁 |
| 文件大小： | 75K |
| 代理商： | SY10E195JC |
Pin
Function
IN/IN
Signal Input
EN
Input Enable
D[0:7]
Mux Select Inputs
Q/Q
Signal Output
LEN
Latch Enable
SET MIN
Minimum Delay Set
SET MAX
Maximum Delay Set
CASCADE
Cascade Signal
DESCRIPTION
FEATURES
PIN NAMES
PROGRAMMABLE
DELAY CHIP
PIN CONFIGURATION
Rev.: E
Issue Date:
Amendment: /0
October, 1998
ClockWorks
SY10E195
SY100E195
I
Up to 2ns delay range
I
Extended 100E V
EE
range of –4.2V to –5.5V
I
≈
20ps/digital step resolution
I
>1GHz bandwidth
I
On-chip cascade circuitry
I
75Kk
input pulldown resistor
I
Fully compatible with Motorola MC10E/100E195
I
Available in 28-pin PLCC package
The SY10/100E195 are programmable delay chips
(PDCs) designed primarily for clock de-skewing and timing
adjustment. They provide variable delay of a differential
ECL input transition.
The delay section consists of a chain of gates
organized as shown in the logic diagram. The first two
delay elements feature gates that have been modified to
have delays 1.25 and 1.5 times the basic gate delay of
approximately 80ps. These two elements provide the
E195 with a digitally-selectable resolution of
approximately 20ps. The required device delay is selected
by the seven address inputs D[0:6], which are latched
on-chip by a high signal on the latch enable (LEN) control.
If the LEN signal is either LOW or left floating, then the
latch is transparent.
Because the delay programmability of the E195 is
achieved by purely differential ECL gate delays, the
device will operate at frequencies of >1GHz, while
maintaining over 600mV of output swing.
The E195 thus offers very fine resolution, at very high
frequencies, selectable entirely from a digital input,
allowing for very accurate system clock timing.
An eighth latched input, D
7
, is provided for cascading
multiple PDCs for increased programmable range. The
cascade logic allows full control of multiple PDCs, at the
expense of only a single added line to the data bus for
each additional PDC, without the need for any external
gating.
18
17
16
15
14
13
12
5
6
7
8
9
10 11
26
27
28
1
2
3
4
TOP VIEW
PLCC
J28-1
25 24 23 22 21 20 19
D
4
D
5
D
6
D
7
D
2
D
3
N
D
1
D
0
LEN
V
EE
IN
IN
V
BB
N
N
S
S
C
E
C
NC
NC
V
CC
V
CCO
Q
Q
V
CCO
1
相關PDF資料 |
PDF描述 |
|---|---|
| SY10E195JCTR | PROGRAMMABLE DELAY CHIP |
| SY100E195 | Programmable Delay Chip(可編程延遲芯片) |
| SY10E195 | Programmable Delay Chip(可編程延遲芯片) |
| SY10E196JCTR | PROGRAMMABLE DELAY CHIP WITH ANALOG INPUT |
| SY100E196 | Programmable Delay Chip with Analog Input(可編程延遲芯片（帶邏輯輸入）) |
相關代理商/技術參數 |
參數描述 |
|---|---|
| SY10E195JC TR | 功能描述:IC DELAY LINE 128TAP 28-PLCC RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 延遲線 系列:10E, Precision Edge® 標準包裝:2,500 系列:- 標片/步級數:- 功能:多個，不可編程 延遲到第一抽頭:10ns 接頭增量:- 可用的總延遲:10ns 獨立延遲數:4 電源電壓:4.75 V ~ 5.25 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:14-SOIC（0.154"，3.90mm 寬） 供應商設備封裝:14-SOIC 包裝:帶卷 (TR) |
| SY10E195JZ | 功能描述:延遲線/計時元素 Programmable Delay Chip (Lead Free) RoHS:否 制造商:Micrel 功能:Active Programmable Delay Line 傳播延遲時間:1000 ps 工作溫度范圍: 封裝 / 箱體:QFN-24 封裝:Tube |
| SY10E195JZ TR | 功能描述:延遲線/計時元素 Programmable Delay Chip (Lead Free) RoHS:否 制造商:Micrel 功能:Active Programmable Delay Line 傳播延遲時間:1000 ps 工作溫度范圍: 封裝 / 箱體:QFN-24 封裝:Tube |
| SY10E196JC | 功能描述:IC DELAY LINE 7TAP 28-PLCC RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 延遲線 系列:10E, Precision Edge® 標準包裝:2,500 系列:- 標片/步級數:- 功能:多個，不可編程 延遲到第一抽頭:10ns 接頭增量:- 可用的總延遲:10ns 獨立延遲數:4 電源電壓:4.75 V ~ 5.25 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:14-SOIC（0.154"，3.90mm 寬） 供應商設備封裝:14-SOIC 包裝:帶卷 (TR) |
| SY10E196JZ | 功能描述:IC DELAY LINE 7TAP 28-PLCC RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 延遲線 系列:10E, Precision Edge® 標準包裝:2,500 系列:- 標片/步級數:- 功能:多個，不可編程 延遲到第一抽頭:10ns 接頭增量:- 可用的總延遲:10ns 獨立延遲數:4 電源電壓:4.75 V ~ 5.25 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:14-SOIC（0.154"，3.90mm 寬） 供應商設備封裝:14-SOIC 包裝:帶卷 (TR) |
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