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參數資料
| 型號： | SY69952ZH |
| 廠商： | MICREL INC |
| 元件分類： | 數字傳輸電路 |
| 英文描述： | OC-3/STS-3 CLOCK RECOVERING TRANSCEIVER |
| 中文描述： | TRANSCEIVER, PDSO28 |
| 封裝： | 0.300 INCH, LEAD FREE, SOIC-28 |
| 文件頁數： | 1/8頁 |
| 文件大小： | 108K |
| 代理商： | SY69952ZH |
SY69952
1
Micrel, Inc.
M9999-062805
hbwhelp@micrel.com or (408) 955-1690
DESCRIPTION
FEATURES
SY69952
A complete ATM compatible single chip Transmitter
and Receiver
Seamless operation with PMC-Sierra PM5345, VLSI
VNS67200, Ig
T WAC-013-B/WAC-413-A and
NEC
μPD98402 UNI Processors
Supports clock and data recovery from 51.84Mbps
or 155.52Mbps NRZ or NRZI data stream
155.52MHz clock multiplication from 19.44MHz
source or 51.84MHz clock multiplication from
6.48MHz source
Line Receiver Inputs: No external buffering needed
Differential output buffering
Link Status Indication
Loop-back testing
100K ECL compatible I/O
Single +5 volt power supply
Replacement for Cypress CY7B952
The SY69952 complies with Bellcore, ITU/CCITT and
ANSI specifications
Available in 28-pin SOIC package
Micrel's SY69952 contains fully integrated transmitter
and receiver functions designed to provide clock recovery
and generation for either 51.84Mbit/s OC/STS-1 or
155.52Mbps OC/STS-3 SONET/SDH (SY69952) and ATM
applications.
On-chip clock generation is performed by a low-jitter
phase-locked loop (PLL) allowing use of 19.44MHz
reference for 155.52MHz generation or a 6.48MHz
reference for 51.84MHz generation. Clock recovery is
performed by synchronizing the on-chip VCO directly to
the incoming data stream.
The SY69952 meets the jitter compliance criteria of
Bellcore, ITU/CCITT and ANSI standards. Low jitter is
ensured by Micrel's advanced PLL technology and
positive ECL (PECL) I/O.
Micre's circuit design techniques coupled with
ASSET bipolar technology result in ultra-fast
performance with low noise and low power dissipation.
OC-3/STS-3
CLOCK RECOVERING
TRANSCEIVER
FUNCTIONAL BLOCK DIAGRAM
PLL
PLL
x8
REFCLK+
REFCLK-
PLL1+
PLL1-
ROUT+
ROUT-
RIN+
RIN-
TOUT+
TOUT-
RCLK+
RCLK-
RSER+
RSER-
TSER+
TSER-
TCLK+
TCLK-
MODE
PLL2+
PLL2-
LOOP
LFI
CD
Rev.: N
Issue Date:
Amendment: /0
June 2005
ASSET is a trademark of Micrel, Inc.
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| SY87700ALZG | Low-Power, 3.3V, 32Mbps to 208Mbps AnyRate Clock and Data Recovery |
| SY87700LHG | 3.3V 32-175Mbps AnyRate CLOCK AND DATA RECOVERY |
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相關代理商/技術參數 |
參數描述 |
|---|---|
| SY69952ZH TR | 功能描述:計時器和支持產品 OC-3/STS-3 Clock Recovering Transceiver (Green) RoHS:否 制造商:Micrel 類型:Standard 封裝 / 箱體:SOT-23 內部定時器數量:1 電源電壓-最大:18 V 電源電壓-最小:2.7 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝:Reel |
| SY6BA9A | 制造商:APEM 功能描述:BA9S 6VAC/DC YELLOW LED |
| SY-6-K | 功能描述:低信號繼電器 - PCB SIGNAL RoHS:否 制造商:NEC 觸點形式:2 Form C (DPDT-BM) 觸點電流額定值: 線圈電壓:5 V 最大開關電流:1 A 線圈電流:1 A 線圈類型:Non-Latching 功耗:140 mW 端接類型:SMT 絕緣: 介入損耗: |
| SY-6W-K | 功能描述:低信號繼電器 - PCB SIGNAL RoHS:否 制造商:NEC 觸點形式:2 Form C (DPDT-BM) 觸點電流額定值: 線圈電壓:5 V 最大開關電流:1 A 線圈電流:1 A 線圈類型:Non-Latching 功耗:140 mW 端接類型:SMT 絕緣: 介入損耗: |
| SY7/8TF | 制造商:UNBRANDED 功能描述:BEARING PILLOW UNIT |
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