參數資料
| 型號： | SY89251VMG TR |
| 廠商： | Micrel Inc |
| 文件頁數： | 1/7頁 |
| 文件大小： | 0K |
| 描述： | IC RCVR ENH DIFF PECL/ECL 8-MLF |
| 標準包裝： | 1 |
| 系列： | SY89 |
| 邏輯類型： | 差分接收器 |
| 電源電壓： | 3 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-VFDFN 裸露焊盤，8-MLF? |
| 供應商設備封裝： | 8-MLF?（2x2） |
| 包裝： | 標準包裝 |
| 產品目錄頁面： | 1090 (CN2011-ZH PDF) |
| 其它名稱： | 576-3500-6 |
SY89251V
Enhanced Differential Receiver
Micrel Inc. 2180 Fortune Drive San Jose, CA 95131 USA tel +1 (
408) 944-0800 fax + 1 (408) 474-1000 http://www.micrel.com
June 2010
M9999-060410-A
hbwhelp@micrel.com or (408) 955-1690
General Description
The SY89251V is a differential PECL/ECL receiver/buffer
in a space saving (2mm x 2mm) DFN package. The device
is functionally equivalent to the SY100EL16VC, except for
an active HIGH enable pin and a 70% smaller footprint. It
is also equivalent to the SY89250V, except for an active
HIGH enable pin. It provides a VBB output for either
single-ended application or as a DC bias for AC-coupling
to the device.
The
SY89251V
provides
an
EN
input
which
is
synchronized with the data input (D) signal in a way that
provides glitchless gating of the QHG and /QHG outputs.
When the EN signal is HIGH, the input is passed to the
outputs and the data output equals the data input. When
the data input is HIGH and the EN goes LOW, it will force
the QHG LOW and the /QHG HIGH on the next negative
transition of the data input. If the data input is LOW when
the EN goes LOW, the next data transition to a HIGH is
ignored and QHG remains LOW and /QHG remains HIGH.
The next positive transition of the data input is not passed
on to the data outputs under these conditions. The QHG
and /QHG outputs remain in their disabled state as long as
the EN input is held LOW. The EN input has no influence
on the /Q output and the data input is passed on (inverted)
to this output whether EN is HIGH or LOW. This
configuration is ideal for crystal oscillator applications,
where the oscillator can be free running and gated on and
off synchronously without adding extra counts to the
output.
Datasheets and support documentation can be found on
Micrel’s web site at: www.micrel.com.
Features
3.3V and 5V power supply options
250ps propagation delay
Very high voltage gain
Ideal for pulse amplifier and limiting amplifier
applications
Data synchronous enable/disable (EN) on Q
HG and
/Q
HG provides for complete glitchless gating of the
outputs
Ideal for gating timing signals
Complete solution for high quality, high frequency
crystal oscillator applications
Available in an ultra-small 8-pin (2mm x 2mm)
DFN package
Applications
Oscillator modules
___________________________________________________________________________________________________________
Block Diagram
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