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參數資料
| 型號： | SY89871U |
| 廠商： | Micrel Semiconductor,Inc. |
| 英文描述： | 2.5GHz ANY DIFF. IN-TO-LVPECL PROGRAMMABLE CLOCK DIVIDER/ FANOUT BUFFER WI/INTERNAL TERMINATION |
| 中文描述： | 2.5GHz的任何微分。在對可編程的LVPECL時鐘分頻器/扇出緩沖器威斯康星/內部終端 |
| 文件頁數： | 1/10頁 |
| 文件大?。?/td> | 168K |
| 代理商： | SY89871U |
1
Precision Edge
Precision Edge
SY89871U
Micrel
M9999-062904
hbwhelp@micrel.com or (408) 955-1690
DESCRIPTION
I
Two matched-delay outputs:
Bank A: undivided pass-through (QA)
Bank B: programmable divide by
2, 4, 8, 16 (QB0, QB1)
I
Matched delay: all outputs have matched delay,
independent of divider setting
I
Guaranteed AC performance:
>2.5GHz f
MAX
<250ps t
r
/t
f
<670ps t
pd
(matched delay)
<15ps within-device skew
I
Low jitter design
<1ps
rms
cycle-to-cycle jitter
<10ps
pp
total jitter
I
Power supply 3.3V or 2.5V
I
Unique patent-pending input termination and VT pin
for DC-coupled and AC-coupled inputs: any
differential inputs (LVPECL, LVDS, CML, HSTL)
I
TTL/CMOS inputs for select and reset
I
100K EP compatible LVPECL outputs
I
Parallel programming capability
I
Wide operating temperature range: –40
°
C to +85
°
C
I
Available in 16-pin (3mm
×
3mm) MLF package
FEATURES
APPLICATIONS
I
OC-3 to OC-192 SONET/SDH applications
I
Transponders
I
Oscillators
I
SONET/SDH line cards
Rev.: C
Issue Date:
Amendment: /0
June 2004
The SY89871U is a 2.5V/3.3V LVPECL output precision
clock divider capable of accepting a high-speed differential
clock input (AC or DC-coupled) CML, LVPECL, HSTL or
LVDS clock input signal and dividing down the frequency
using a programmable divider ratio to create a frequency-
locked lower speed version of the input clock (Bank B).
Available divider ratios are 2, 4, 8 and 16. In a typical
622MHz clock system this would provide availability of
311MHz, 155MHz, 77MHz, or 38MHz auxiliary clock
components.
The differential input buffer has a unique internal
termination design that allows access to the termination
network through a VT pin. This feature allows the device to
easily interface to different logic standards. A V
REF-AC
reference is included for AC-coupled applications.
The SY89871U includes two phase-matched output
banks. Bank A (QA) is a frequency-matched copy of the
input. Bank B (QB0, QB1) is a divided down output of the
input frequency. Bank A and Bank B maintain a matched
delay independent of the divider setting.
All support documentation can be found on Micrel’s web
site at www.micrel.com.
FUNCTIONAL BLOCK DIAGRAM
Precision Edge
2.5GHz ANY DIFF. IN-TO-LVPECL
PROGRAMMABLE CLOCK DIVIDER/
FANOUT BUFFER W/INTERNAL TERMINATION
TYPICAL PERFORMANCE
Precision Edge is a trademark of Micrel, Inc.
MicroeadFrame and MLF are trademarks of Amkor Technology, Inc.
IN
50
50
/IN
S0
S1
QB1
/QB1
QB0
/QB0
QA
/QA
/RESET
V
T
V
REF-AC
Divided
by
2, 4, 8
or 16
Decoder
/QB0
QB0
/QA
QA
QA@622MHz and QB@155.5MHz
4
622MHz
Output
155.5MHz
Output
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相關代理商/技術參數 |
參數描述 |
|---|---|
| SY89871U_07 | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:2.5GHz ANY DIFF. IN-TO-LVPECL PROGRAMMABLE CLOCK DIVIDER |
| SY89871UMG | 功能描述:時鐘驅動器及分配 2.5V/3.3V PECL Output Clock Divider/Fanout (I Temp, Green) RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| SY89871UMG TR | 功能描述:時鐘驅動器及分配 2.5V/3.3V PECL Output Clock Divider/Fanout (I Temp, Green) RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| SY89871UMGTR | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:2.5GHz ANY DIFF. IN-TO-LVPECL PROGRAMMABLE CLOCK DIVIDER |
| SY89871UMI | 功能描述:IC CLOCK BUFF DIVIDER 1:3 16-MLF RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘緩沖器，驅動器 系列:Precision Edge® 標準包裝:1 系列:HiPerClockS™ 類型:扇出緩沖器（分配），多路復用器 電路數:1 比率 - 輸入:輸出:2:18 差分 - 輸入:輸出:是/無 輸入:CML，LVCMOS，LVPECL，LVTTL，SSTL 輸出:LVCMOS，LVTTL 頻率 - 最大:250MHz 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:32-LQFP 供應商設備封裝:32-TQFP（7x7） 包裝:- 其它名稱:800-1923-6 |
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