參數資料
| 型號： | SY89871UMG TR |
| 廠商： | Micrel Inc |
| 文件頁數： | 1/11頁 |
| 文件大小： | 0K |
| 描述： | IC CLOCK BUFF DIVIDER 1:3 16-MLF |
| 標準包裝： | 1,000 |
| 系列： | Precision Edge® |
| 類型： | 扇出緩沖器（分配），除法器 |
| 電路數： | 1 |
| 比率 - 輸入:輸出： | 1:3 |
| 差分 - 輸入:輸出： | 是/是 |
| 輸入： | CML，HSTL，LVDS，LVPECL |
| 輸出： | LVPECL |
| 頻率 - 最大： | 2.5GHz |
| 電源電壓： | 2.375 V ~ 3.63 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-VFQFN 裸露焊盤，16-MLF? |
| 供應商設備封裝： | 16-MLF?（3x3） |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | SY89871UMGTR SY89871UMGTR-ND |
SY89871U
2.5GHz Any Diff. In-To-LVPECL
Programmable Clock Divider/Fanout Buffer
w/ Internal Termination
Precision Edge is a registered trademark of Micrel, Inc
Micre
l Inc. 2180 Fortune Drive San Jose, CA 95131 USA tel +1 (408) 944-0800 fax + 1 (408) 474-1000 http://www.micrel.com
Oct. 1, 2013
M9999-010512-F
hbwhelp@micrel.com or (408) 955-1690
General Description
The SY89871U is a 2.5V/3.3V LVPECL output precision
clock divider capable of accepting a high-speed differential
clock input (AC or DC-coupled) CML, LVPECL, HSTL or
LVDS clock input signal and dividing down the frequency
using a programmable divider ratio to create a frequency-
locked lower speed version of the input clock (Bank B).
Available divider ratios are 2, 4, 8, and 16. In a typical
622MHz clock system this would provide availability of
311MHz, 115MHz, 77MHz, or 38MHz auxiliary clock
components.
The
differential
input
buffer
has
a
unique
internal
termination design that allows access to the termination
network through a VT pin. This feature allows the device to
easily interface to different logic standards. A VREF-AC
reference is included for AC-coupled applications.
The SY89871U includes two phase-matched output banks.
Bank A (QA) is a frequency-matched copy of the input.
Bank B (QB0, QB1) is a divided down output of the input
frequency. Bank A and Bank B maintain a matched delay
independent of the divider setting.
Data sheets and support documentation can be found on
Micrel’s web site at: www.micrel.com.
Typical Performance
Precision Edge
Features
Two matched-delay outputs:
- Bank A: undivided pass-through (QA)
- Bank B: programmable divide by 2, 4, 8, 16 (QB0,
QB1)
Matched delay: all outputs have matched delay,
independent of divider setting
Guaranteed AC performance:
- >2.5GHz fMAX
- <250ps tr/tf
- <670ps tpd (matched delay)
- <15ps within-device skew
Low jitter design
- 231fs RMS phase jitter (Typ)
Power supply 3.3V or 2.5V
Unique patent-pending input termination and VT pin for
DC- and AC- coupled inputs: any differential inputs
(LVPECL, LVDS, CML, HSTL)
TTL/CMOS inputs for select and reset
100K EP compatible LVPECL outputs
Parallel programming capability
Wide operating temperature range: -40°C to +85°C
Available in 16-pin (3mm x 3mm) QFN package
Applications
OC-3 to OC-192 SONET/SDH applications
Transponders
Oscillators
SONET/SDH line cards
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相關代理商/技術參數 |
參數描述 |
|---|---|
| SY89871UMI | 功能描述:IC CLOCK BUFF DIVIDER 1:3 16-MLF RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘緩沖器，驅動器 系列:Precision Edge® 標準包裝:1 系列:HiPerClockS™ 類型:扇出緩沖器（分配），多路復用器 電路數:1 比率 - 輸入:輸出:2:18 差分 - 輸入:輸出:是/無 輸入:CML，LVCMOS，LVPECL，LVTTL，SSTL 輸出:LVCMOS，LVTTL 頻率 - 最大:250MHz 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:32-LQFP 供應商設備封裝:32-TQFP（7x7） 包裝:- 其它名稱:800-1923-6 |
| SY89871UMI TR | 功能描述:IC CLOCK BUFF DIVIDER 1:3 16-MLF RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘緩沖器，驅動器 系列:Precision Edge® 標準包裝:1 系列:HiPerClockS™ 類型:扇出緩沖器（分配），多路復用器 電路數:1 比率 - 輸入:輸出:2:18 差分 - 輸入:輸出:是/無 輸入:CML，LVCMOS，LVPECL，LVTTL，SSTL 輸出:LVCMOS，LVTTL 頻率 - 最大:250MHz 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:32-LQFP 供應商設備封裝:32-TQFP（7x7） 包裝:- 其它名稱:800-1923-6 |
| SY89871UMITR | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:2.5GHz ANY DIFF. IN-TO-LVPECL PROGRAMMABLE CLOCK DIVIDER |
| SY89872U | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:2.5V, 2GHz ANY DIFF. IN-TO-LVDS PROGRAMMABLE CLOCK DIVIDER/FANOUT BUFFER WITH INTERNAL TERMINATION |
| SY89872U_0708 | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:2.5V, 2GHz ANY DIFF. IN-TO-LVDS |
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