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參數資料
| 型號： | T2316407A-70 |
| 廠商： | TM Technology, Inc. |
| 英文描述： | SPST, Low Profile DIP Switches |
| 中文描述： | 4米× 4動態隨機存儲器EDO公司頁面模式 |
| 文件頁數： | 1/14頁 |
| 文件大小： | 136K |
| 代理商： | T2316407A-70 |
TE
CH
tm
DRAM
Preliminary T2316407A
Taiwan Memory Technology, Inc. reserves the right
P. 1
to change products or specifications without notice.
Publication Date: APR 2001
Revision:0.B
T2316405A
4M x 4 DYNAMIC RAM
EDO PAGE MODE
FEATURES
Industry-standard x 4 pinouts and timing
functions
power supply : T2316405A 2.6V(±0.2V)
T2316407A 3.3V(±0.3V)
All device pins are TTL- compatible.
2048-cycle refresh in 32 ms.
Refresh modes: RAS only, CAS BEFORE
RAS (CBR) and HIDDEN.
Extended data-out (EDO) PAGE MODE
access cycle.
OPTION
TIMING
50ns (For T2316407A only) -50
60ns (For T2316407A only) -60
70ns (For T2316407A only) -70
100ns (For T2316405A only) -10
PACKAGE
26/24-pin SOJ
26/24-pin TSOP-II
PIN ARRANGEMENT (
Top View)
MARKING
J
S
I/O1
I/O2
Vcc
NC
A10
A0
A1
A2
A3
26
25
24
23
22
21
18
17
16
15
14
1
2
3
4
5
6
9
10
11
12
13
I/O4
I/O3
CAS
Vss
A8
A7
A6
A5
A4
Vss
OE
A9
WE
RAS
19
8
Vcc
SOJ
&
TSOP-II
GRNERAL DESCRIPTION
The T2316405A and T2316407A is a randomly
accessed solid state memory containing 16,777,216
bits organized in a x 4 configuration. It offers Fast
Page mode with Extended Data Output (EDO).
During READ or WRITE cycles, each of the 4
memory bits (1 bit per I/O) is uniquely addressed
through the 22 address bits, which are entered 11
bits (A0-A10) at a time. RAS latches the first 11
bits and CAS latches the latter 11 bits.
the WE input. A logic HIGH on WE dictates
READ mode while a logic LOW on WE dictates
WRITE mode. During a WRITE cycle, data-in is
latched by the falling edge of
WE
or
CAS
,
whichever occurs last. When WE goes Low prior
to
CAS
going LOW ( EARLY WRITE cycle), the
output pins remain open (High-Z) until the next
CAS cycle.
A READ or WRITE cycle is selected wth
A Late Write or Read-Modify-Write occurs.
When
WE
falls after
CAS
was taken LOW (Late
Write cycle). OE must be taken HIGH to disable
the data-outputs prior to applying input data.
The four data inputs and four data outputs are
routed through four pins using common I/O, and pin
direction is controlled by WE and OE.
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