
TE
CH
tm
SDRAM
FEATURES
3.3V power supply
Clock cycle time : 6 / 7 / 8 / 10 ns
Dual banks operation
LVTTL compatible with multiplexed address
All inputs are sampled at the positive going
edge of system clock
Burst Read Single-bit Write operation
DQM for masking
Auto refresh and self refresh
32ms refresh period (2K cycle)
MRS cycle with address key programs
- CAS Latency ( 2 & 3 )
- Burst Length ( 1 , 2 , 4 , 8 & full page)
- Burst Type (Sequential & Interleave)
Available package type in 50 pin TSOP(II)
and 60-pin CSP.
Operating temperature :
-
-5 ~ +70
°
C
-
-40 ~ +85
°
C
PART NUMBER EXAMPLES
T431616A
Taiwan Memory Technology, Inc. reserves the right
P. 1
to change products or specifications without notice.
Publication Date: DEC. 2000
Revision: C
1M x 16 SDRAM
512K x 16bit x 2Banks Synchronous DRAM
GRNERAL DESCRIPTION
The T431616A is 16,777,216 bits synchronous
high data rate Dynamic RAM organized as
2 x 524,288 words by 16 bits , fabricated with high
performance CMOS technology . Synchronous
design allows precise cycle control with the use of
system clock I/O transactions are possible on every
clock cycle . Range of operating frequencies ,
programmable burst length and programmable
latencies allow the same device to be useful for a
variety of high bandwidth , high performance
memory system applications.
PART NO.
CLOCK
CYCLE TIME
MAX
FREQUENCY
143 MHz
PACKAGE
OPERATING
TEMPERATURE
-5 ~ +70
°
C
-5 ~ +70
°
C
-40 ~ +85
°
C
-40 ~ +85
°
C
T431616A-7S
7ns
TSOP-II
T431616A-7C
T431616A-7SI
7ns
143 MHz
143 MHz
CSP
7ns
TSOP-II
T431616A-7CI
7ns
143 MHz
CSP