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參數(shù)資料
| 型號： | T7295-1 |
| 廠商： | Lineage Power |
| 英文描述： | E3 Integrated Line Receiver(E3 集成線接收器) |
| 中文描述： | 綜合線接收E3展（E3展集成線接收器） |
| 文件頁數(shù)： | 1/14頁 |
| 文件大小： | 321K |
| 代理商： | T7295-1 |
Data Sheet
February 1997
T7295-1 E3 Integrated Line Receiver
Features
I
Fully integrated receive interface for E3 signals
I
Integrated equalization (optional) and timing
recovery
I
Loss-of-signal and loss-of-lock alarms
I
Variable input sensitivity control
I
Single 5 V power supply
Applications
I
Interface to E3 networks
I
CSU/DSU equipment
I
PCM test equipment
I
Fiber-optic terminals
I
Companion device to T7296 transmitter
Description
The T7295-1 E3 Integrated Line Receiver is a fully
integrated receive interface that terminates a bipolar
E3 (34.368 Mbits/s) signal transmitted over coaxial
cable. This device can be used with the T7296 Inte-
grated Line Transmitter.
The device provides the functions of receive equal-
ization (optional), automatic-gain control (AGC),
clock recovery and data retiming, and loss-of-signal
and loss-of-frequency-lock detection. The digital sys-
tem interface is dual rail, with received positive and
negative 1s appearing as unipolar digital signals on
separate output leads. The on-chip equalizer is
designed for cable losses up to 15 dB. The receive
input has a variable input sensitivity control, provid-
ing three different sensitivity settings. High input sen-
sitivity allows for significant amounts of flat loss
within the system. Figure 1 shows the block diagram
of the device.
The T7295-1 device is manufactured by using linear
CMOS technology and is packaged in a 20-pin, plas-
tic DIP or 20-pin, plastic SOJ package for surface
mounting. Figure 2 shows the pin layout for both
package types.
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