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參數資料
| 型號： | T7688 |
| 廠商： | Lineage Power |
| 英文描述： | 5.0 V E1/CEPT Quad Line Interface(5.0 V E1/CEPT四線接口) |
| 中文描述： | 5.0V的E1/CEPT四線接口（5.0V的E1/CEPT四線接口） |
| 文件頁數： | 1/38頁 |
| 文件大小： | 577K |
| 代理商： | T7688 |
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Data Sheet
May 1998
T7688 5.0 V E1/CEPT Quad Line Interface
Features
I
Four fully integrated E1 line interfaces
I
Includes all driver, receiver, equalization, clock
recovery, and jitter attenuation functions
I
Ultralow power consumption
I
Robust operation for increased system margin
I
High interference immunity
I
On-chip transmit equalization for improved
sensitivity
I
Low-impedance drivers for reduced power
consumption
I
Selectable transmit or receive jitter attenuation/
clock smoothing
I
3-state transmit drivers
I
High-speed, microprocessor interface
I
Automatic transmit monitor function
I
Per-channel powerdown
I
For use in systems that are compliant with ITU-T
G.703, G.732, G.735-9, G.775, G.823-4, and I.431
I
Common transformer for transmit/receive
I
Fine-pitch (25 mil spacing) surface-mount
package, 100-pin bumpered quad flat pack
I
–40
°
C to +85
°
C operating temperature range
Applications
I
SONET/SDH multiplexers
I
Asynchronous multiplexers (M13)
I
Digital access cross connects (DACs)
I
Channel banks
I
Digital radio base stations, remote wireless
modules
I
PBX interfaces
Description
The T7688 is a fully integrated quad line interface
containing four transmit and receive channels for use
in European (E1/CEPT) applications. The device has
many of the same functions as the Lucent Technolo-
gies Microelectronics Group T7290A and provides
additional flexibility for the system designer.
Included is a parallel microprocessor interface that
allows the user to define the architecture, initiate
loopbacks, and monitor alarms. The interface is com-
patible with many commercially available micropro-
cessors.
The receiver performs clock and data recovery using
a fully integrated digital phase-locked loop. This digi-
tal implementation prevents false-lock conditions
that are common when recovering sparse data pat-
terns with analog phase-locked loops. Equalization
circuitry in the receiver guarantees a high level of
interference immunity. As an option, the raw sliced
data (no retiming) can be output on the receive data
pins.
Transmit equalization is implemented with low-
impedance output drivers that provide shaped wave-
forms to the transformer, guaranteeing template
conformance. The quad device will interface to line
impedances of 75
or 120
for CEPT operation.
A selectable jitter attenuator may be placed in the
receive signal path for low-bandwidth line-
synchronous applications, or it may be placed in the
transmit path for multiplexer applications where
CEPT signals are demultiplexed from higher rate sig-
nals. The jitter attenuator will perform the clock
smoothing required on the resulting demultiplexed
gapped clock.
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